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Altera_Forum
Honored Contributor I
743 Views

NiosII SPI read problem

Hello everyone! 

 

I am using the SPI core in niosII to connect my fpga to peripheral and I am experiencing problems only when I try to read data from the peripheral. I first write certain data to my peripheral and then read it back. The results only match in certain cases, but I know that the data was written to it correctly in all cases. By writing to status register of the peripheral I set its sampling rate. That's how I know that the data was written correctly. For instance, when I write to the status register 0x01 and then read back, the written and read data match. But when I write 0x02, the read data is 0x03, but I see that my peripheral samples data faster. Also, when I write 0x03, I get back also 0x03, but it samples faster than in previous case. When I write 0x04, 0x05, 0x06 and 0x07, I read back 0x07. When I write 0x08, 0x09, I read back 0x0F. So, it appears to me that the problem might lie in the configuration of the input pin used as MISO pin as it struggles to put it low after the high voltage level. In the assignment editor I configured MISO pin as input tri-stated, but it doesn't help. Does anyone have any suggestions where the problem comes from? 

 

Thanks very much in advance!
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2 Replies
Altera_Forum
Honored Contributor I
35 Views

If You're using SPI as master, then MISO pin must be INPUT (Master In Slave Out). Anyway, the clocking rate of the SCK signal is determined in core parameters and are not changeable afaik, so I doubt it's a speed issue.

Altera_Forum
Honored Contributor I
35 Views

Thanks for the reply. I don't think either it is a speed issue. My SCK should be 10MHz and reducing the speed didn't solve the problem.

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