No EPCS Layout data - looking for section [EPCS-C84017]

[Altera_Forum]

I am trying to program a set of boards using the nios2-flash-programmer. They boards have an EP4CE10F17CN7 fpga with the EPCS64N configuration ROM. When I try to program it (even just trying to erase the epcs device) using the command: 

nios2-flash-programmer --base=0x0 --epcs  I get the error: No EPCS Layout data - looking for section [EPCS-C84017] Unable to use the EPCS device.  I have searched for this code and cannot find it.  I have also created a "memory test" BSP and Application from the Nios2 and it successfully runs the memory test on the EPCS device which I believe indicates that I have successful FPGA/EPCS device communication.  I appreciate any assistance to get me through this problem.

[Altera_Forum]

--- Quote Start ---  I am trying to program a set of boards using the nios2-flash-programmer. They boards have an EP4CE10F17CN7 fpga with the EPCS64N configuration ROM. When I try to program it (even just trying to erase the epcs device) using the command: nios2-flash-programmer --base=0x0 --epcs  I get the error: No EPCS Layout data - looking for section [EPCS-C84017] Unable to use the EPCS device.  I have searched for this code and cannot find it.  I have also created a "memory test" BSP and Application from the Nios2 and it successfully runs the memory test on the EPCS device which I believe indicates that I have successful FPGA/EPCS device communication.  I appreciate any assistance to get me through this problem.  --- Quote End ---    An update:  I followed the method to program the Nios Image directy from the jtag per the following steps:  solution id: rd10132010_126 last modified: Sep 11, 2012 product category: Devices product area: Configuration (FPGA) product sub-area: Active Serial (AS) device family: MISC  Description[/B]The method used to create a .jic file with a Nios® II hardware and software image is as follows. 1. Create a flash file from a .sof file: sof2flash --input=<hwimage>.sof --output=hwimage.flash --epcs --verbose 2. Create a flash file from a ,elf file: elf2flash --input=<elf file>.elf --output=swimage.flash --epcs --after=hwimage.flash --verbose  3. Convert the .flash image into a.hex file: nios2-elf-objcopy --input-target srec --output-target ihex mysw.flash mysw.hex 4. In the Quartus® II software, open File > Convert Programming Files > Set the programming file as JTAG Indirect Configuration File (.jic).  6. Select the correct size EPCS device in the Configuration pull-down 7. Name your output .jic file 8. Click Flash Loader below, and select Add Device on the right hand side 9. Select your FPGA device from the list 10. Click SOF Data, and select Add File, and select your .sof file 11. Click Add Hex data, select Relative addressing, and select your .hex file created above 12. Now push generate. You should verify that the generated .map file has Page_0 at a start address of 0x0, and the hex file at a start address 1 after the end address of Page_0 13. Now in the Quartus II Programmer, select Add File and select your .jic file. Check the Program box next to the .jic file, and push Start   [/B]And the image did write to the memory and when the board's power was cycled, the correct program came up (for both the FPGA and the NIOS core).  I then went back to program via the nios2-flash-programmer, and it give me the same error message (as the originally specified).  Thank you in advance  Michael