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Altera_Forum
Honored Contributor I
781 Views

No network activity

I'm writing an application in uc/osII which uses the iniche stack for network communications. My application runs successfully on the Altera provided sss example, however, once transferring to a new board design, the ethernet doesn't seem to be working. Below is a print out of the application, upon initialization. 

 

 

 

Your Ethernet MAC address is 00:07:ed:ff:cd:15 

Static IP Address is 192.168.1.234 

prepped 2 interfaces, initializing... 

[tse_mac_init] 

INFO : TSE MAC 0 found at address 0x0c005000 

INFO : PHY Marvell 88E1111 found at PHY address 0x12 of MAC Group[0] 

INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0] 

INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... 

INFO : PHY[0.0] - Auto-Negotiation PASSED 

MARVELL : Mode changed to RGMII/Modified MII to Copper mode 

MARVELL : Enable RGMII Timing Control 

MARVELL : PHY reset 

INFO : PHY[0.0] - Checking link... 

INFO : PHY[0.0] - Link not yet established, restart auto-negotiation... 

INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... 

INFO : PHY[0.0] - Auto-Negotiation PASSED 

INFO : PHY[0.0] - Link established 

INFO : PHY[0.0] - Speed = 100, Duplex = Full 

OK, x=0, CMD_CONFIG=0x00000000 

 

 

MAC post-initialization: CMD_CONFIG=0x04000203 

[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created 

mctest init called 

IP address of : 192.168.1.234 

INET> Created "Inet main" task (Prio: 2) 

Created "clock tick" task (Prio: 3) 

 

It seems like the tse_mac is being setup correctly. I know it seems obvious that there's some issue with the new design, but I'm not sure where to start with debugging the problem. Here is the tse_mac setup, from the system.h file. 

 

/* 

* ethernet_subsystem_tse_mac configuration 

*/ 

 

# define ALT_MODULE_CLASS_ethernet_subsystem_tse_mac triple_speed_ethernet# define ETHERNET_SUBSYSTEM_TSE_MAC_BASE 0xc005000# define ETHERNET_SUBSYSTEM_TSE_MAC_ENABLE_MACLITE 0# define ETHERNET_SUBSYSTEM_TSE_MAC_FIFO_WIDTH 32# define ETHERNET_SUBSYSTEM_TSE_MAC_IRQ -1# define ETHERNET_SUBSYSTEM_TSE_MAC_IRQ_INTERRUPT_CONTROLLER_ID -1# define ETHERNET_SUBSYSTEM_TSE_MAC_IS_MULTICHANNEL_MAC 0# define ETHERNET_SUBSYSTEM_TSE_MAC_MACLITE_GIGE 0# define ETHERNET_SUBSYSTEM_TSE_MAC_MDIO_SHARED 0# define ETHERNET_SUBSYSTEM_TSE_MAC_NAME "/dev/ethernet_subsystem_tse_mac"# define ETHERNET_SUBSYSTEM_TSE_MAC_NUMBER_OF_CHANNEL 1# define ETHERNET_SUBSYSTEM_TSE_MAC_NUMBER_OF_MAC_MDIO_SHARED 1# define ETHERNET_SUBSYSTEM_TSE_MAC_PCS 0# define ETHERNET_SUBSYSTEM_TSE_MAC_PCS_ID 0u# define ETHERNET_SUBSYSTEM_TSE_MAC_PCS_SGMII 0# define ETHERNET_SUBSYSTEM_TSE_MAC_RECEIVE_FIFO_DEPTH 2048# define ETHERNET_SUBSYSTEM_TSE_MAC_REGISTER_SHARED 0# define ETHERNET_SUBSYSTEM_TSE_MAC_RGMII 1# define ETHERNET_SUBSYSTEM_TSE_MAC_SPAN 1024# define ETHERNET_SUBSYSTEM_TSE_MAC_TRANSMIT_FIFO_DEPTH 2048# define ETHERNET_SUBSYSTEM_TSE_MAC_TYPE "triple_speed_ethernet"# define ETHERNET_SUBSYSTEM_TSE_MAC_UNASSIGNED "unassigned"# define ETHERNET_SUBSYSTEM_TSE_MAC_USE_MDIO 1 

 

thanks, 

Drew
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Altera_Forum
Honored Contributor I
29 Views

How is the TSE connected to the PHY chip in the new design? 

It seems that the PHY is synchronizing at 100Mbps and not gigabit. Was it the same on the first design? Did you connect the clocks accordingly, and at the right frequencies? 

The next step to debug the problem is to put some signaltap probes on the RGMII interface and see what is happening there.
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