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Altera_Forum
Honored Contributor I
1,952 Views

Not able to interface SDRAM with nios Processor

I have made a system with Nios processor, JTAG-UART, SDRAM(8MB), Clock Signal IP core, on chip memory. I am not able to implement the hello World Program. The nios console doesnt show anything except for : 

 

USB-Blaster on localhost[USB-0] device ID:1 instance ID-0 name JTAG-UART_0 

 

The problem is with the SDRAM because the system working fine without it and printing hello World. Earlier posts suggest checking the clock skew but I havent used the PLL. The clock signal IP core( clock signals for DE-series board Pheripherals) is supposed to take of the skew on its own. Any suggestion on what could be wrong ?
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8 Replies
Altera_Forum
Honored Contributor I
26 Views

What dev board are you using? It should have come with an example that uses SDRAM. Use that as your starting point. 

 

If that doesn't work, load a pre-built .sof file that uses SDRAM to verify that your hardware is working.
Altera_Forum
Honored Contributor I
26 Views

Gal is right... what board are you using actually?

Altera_Forum
Honored Contributor I
26 Views

I am using the DE2 board. I tried to follow the step given in their example but their example is using a PLL.

Altera_Forum
Honored Contributor I
26 Views

The design example uses a PLL for good reason. The clock out to the SDRAM will need to be phase shifted with respect to the clock driving the logic. 

 

 

--- Quote Start ---  

The clock signal IP core( clock signals for DE-series board Pheripherals) is supposed to take of the skew on its own 

--- Quote End ---  

 

I'm not sure what you mean by this. What 'IP core' is it referring to if it's not a PLL? 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
26 Views

There is a clock signals IP core in the University Programs Module that I am using.  

 

This is what the description says in the tutorial document: 

 

"The clock skew depends on physical characteristics of the DE2 board. For proper operation of the SDRAM chip,it is necessary that its clock signal, DRAM_CLK, leads the Nios II system clock, CLOCK_50, by 3 nanoseconds.This can be accomplished by using a phase-locked loop (PLL) circuit which can be manually created using the MegaWizard plug-in. It can also be created automatically using the Clock Signals IP core provided by the Altera University Program "
Altera_Forum
Honored Contributor I
26 Views

The "Clock Signals IP core" is a wrapper, which instantiates a PLL with settings specific to the hardware you're using. So, you are using a PLL it's just hidden behind this IP core. 

 

All I can suggest is that you revisit all the settings you are presented with in configuring that IP core. Alternatively, you could try instantiating the PLL directly. This will require more settings. However, you will be able to take these from the reference design available for the dev board. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
26 Views

I would recommend not using the university program core and starting with a known working SDRAM example. Test the example first to make sure your hardware is good. 

 

If you do want to stay with the university core, make sure you verify that the core you are using is designed for the exact development board you are using. This includes the ram chips as they can change during a production run. The settings on an SDRAM controller depend on the exact ram chip being used as well as the geometry of the traces on the board. A core configured with the settings for a different board won't function correctly.
Altera_Forum
Honored Contributor I
26 Views

Unfortunately, there is no way to go around the SDRAM clock without using PLL to generate the proper SDRAM clk.