OS on Cyclone 5 HPS without hard memory controller

[Altera_Forum]

I have a question regarding selecting a chip for a project. The client requests one without a hard memory controller (5CSEB...), but I couldn't find a dev kit with the exact same chip, so I have no choice but to go with one that has a hard memory controller. From what I read in the "Cyclone 5 device overview" datasheet, the hard memory controller is only for the FPGA, the HPS having its own controller. However, the HPS reference manual states that the memory controllers are somehow shared. 

 My questions are 1. Does the HPS have a hard memory controller of its own? 2. If not, does the chip not having a hard memory controller mean I cannot run an OS that requires one (i.e. Linux), without resorting to adding IP cores to the FPGA? 3. Can I somehow disable/not use the hard memory controller from a chip that has one, so that it will behave the same as the chip the client requests?  Thanks

[Altera_Forum]

Hi, for Cyclone V (FPGA side) you can choose to use "soft" memory controller IP (like the UniPHY IP). But even on chip with built in hard memory controller, you can choose to not use it, should you decide so. For Cyclone V HPS, yes the HPS portion has its own memory controller that is not shared with the FPGA. 

 The trick is that you can use the FPGA to access the memory controller in the HPS, via an interface called FPGA-to-SDRAM.   So to answer your question: 1. Yes 2. You can run Linux on the HPS without needing to use any IP cores in the FPGA, should you choose to. 3. Yes you can do this. Just make sure that you are connecting the pins correctly (the hard memory controller requires a fixed memory pin locations - so make sure you don't connect the memory to these location should you choose to use a soft controller)