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Altera_Forum
Honored Contributor I
793 Views

Offset in received SPI data

Hi, 

I am currently working on a project in which altera FPGA is the slave SPI.  

 

Transferred data is 21 words long. Each test packet looks like: 

0x0001, 0x0002, 0x0003,...,0x0021, and it could be seen as well by SignalTap. 

 

Unfortunately, my spi_irq_handler in SPI slave return data like: 

0x0021, 0x0001, 0x0002, ..., 0x0020 

 

The driver source code is very simple: 

void altera_avalon_spi_init(altera_avalon_spi_state* sp, 

int irq_controller_id, int irq) 

{ IOWR_ALTERA_AVALON_SPI_CONTROL(sp->base, ALTERA_AVALON_SPI_CONTROL_IRRDY_MSK); 

 

alt_ic_isr_register(irq_controller_id, irq, altera_avalon_spi_irq, 

sp, NULL); 

 

static void altera_avalon_spi_irq(void* context) 

{ altera_avalon_spi_state* sp = (altera_avalon_spi_state *)context; 

alt_u32 base = sp->base; 

alt_u16 * prd = read_data; 

alt_u16 * read_end = prd + read_length; 

alt_u32 status; 

 

for ( ; ; ) 

do 

status = IORD_ALTERA_AVALON_SPI_STATUS(base); 

while ((status & ALTERA_AVALON_SPI_STATUS_RRDY_MSK) == 0); 

 

if ((status & ALTERA_AVALON_SPI_STATUS_RRDY_MSK) != 0) 

alt_u32 rxdata = IORD_ALTERA_AVALON_SPI_RXDATA(base); 

*prd++ = (alt_u16)rxdata; 

if (prd == read_end) 

break; 

 

I tried also to clear RXBUFFER by IORD_ALTERA_AVALON_SPI_RXDATA(base) just before every packet, but it doesn't work anyway.. 

 

Can anyone please help me understand what's happening?
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5 Replies
Altera_Forum
Honored Contributor I
50 Views

This is a 3-wire SPI, right?

Altera_Forum
Honored Contributor I
50 Views

Yes,  

MOSI, MISO, CLK are used. 

(SS of course is used also)
Altera_Forum
Honored Contributor I
50 Views

This may be because the master is repeatedly sending 1 to 21 and the nios slave read the value 21 first followed by the remaining  

 

Are you getting the same result always are its time shifted
Altera_Forum
Honored Contributor I
50 Views

SPI master is repeatedly sending 1,2,..21 with pause between packets. 

And the result is always the same. 

 

The only unusual feature of the master is that SS is toggled on every word transmitted. 

I tried to add IORD_ALTERA_AVALON_SPI_RXDATA(base) before every packet handling. In that case the 1st packet is OK (0x0001, 0x002, ...0x0021), but others are corrupted.
Altera_Forum
Honored Contributor I
50 Views

The SPI master functions should me similar to NIOS SPI master specification or else NIOS slave cant decode correctly  

 

I think the CS should be low until all the bits are recieved and should go high
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