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New Contributor I
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On-Chip Flash Intel FPGA IP for Max 10

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I am trying to build a NIOSII based SOC system with all IP's reused from the IP catalog. It is being built for the DECA evaluation board (with Max 10, 10M50DAF484C6G FPGA ). OnChip flash IP is showing below error while implementation step. I have tried with multiple settings of Configuration Mode and Flash Memory Access modes. Attaching a couple of screen shots here for reference. I get the below error message when running the fitting step in the Quartus II software (Latest 18.1 SW). Attaching the Quartus run log. Elaboration step doesn't show any problems. How to go past this issue?

Error (14740): Configuration mode on atom "PH_SOC:PH_SOC_inst|altera_onchip_flash:ufm_flash|altera_onchip_flash_block:altera_onchip_flash_block|ufm_block" does not match the project setting. Update and regenerate the Qsys system to match the project setting.

Error: Quartus Prime Fitter was unsuccessful. 1 error, 1 warning

Error: Peak virtual memory: 5178 megabytes

Error: Processing ended: Tue Oct 09 10:00:54 2018

Error: Elapsed time: 00:00:07

Error: Total CPU time (on all processors): 00:00:05

Error (293001): Quartus Prime Full Compilation was unsuccessful. 3 errors, 446 warnings

 

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New Contributor I
102 Views

Okay found the option to match this. Its embeded deep inside the Quartus settings menu.

Open Device/Board settings, then Device and pin settings, then select configuration. Here the setting has to match the setting selected in QSYS Configuration Mode settings. It took a while to figure out. See attachment for this screenshot of the setting.

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Highlighted
New Contributor I
103 Views

Okay found the option to match this. Its embeded deep inside the Quartus settings menu.

Open Device/Board settings, then Device and pin settings, then select configuration. Here the setting has to match the setting selected in QSYS Configuration Mode settings. It took a while to figure out. See attachment for this screenshot of the setting.

View solution in original post