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One question about nios2_multiprocessor

Altera_Forum
Honored Contributor II
801 Views

tt_nios2_multiprocessor_tutorial provides an example design which builds a multiprocessor system containing three processors that all share a memory buffer.Using the  

Nios II Integrated Development Environment (IDE), we can create and debug three software projects, one for each processor in the system. My question is:can I create only one software project for these three processors? Thanks a lot in advance!
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3 Replies
Altera_Forum
Honored Contributor II
94 Views

If you expose the reset lines to the subsiduary processors and connect them to (say) a pio slave that the main cpu has access to you can load a single image that contains code for all the cpus. 

Once the first cpu has initialised any shared areas, it can take the other cpu out of reset. 

You probably can't use the jtag debuger or uart on the other cpus. 

 

If you are using theother cpus for simple tasks the code required can be tiny - ignore all the altera supplied support, just initialise the %sp and %gp registers and jump directly to the user C code.
Altera_Forum
Honored Contributor II
94 Views

my true purpose is that i want to use microC/OS to control all the cpus(a least two), using microC/OS distribute tasks among all the cpus. 

for example, in one moment, task_A runing on cpu_1, task_b runing on cpu_2. if task_A finishes or is interrupted, microC/OS schedules task_C to cpu_1. 

 

so I want to know how to modify _OSCtxSw function(and other function in OS_CPU_A) allows it to complete the scheduling work in all cpus.
Altera_Forum
Honored Contributor II
94 Views

To do that you need a full multi-cpu aware operating system and hardware that supports locked 'read modify write' bus operations for locks (ok, you can use dekker's algorythm, but it isn't ideal for normal locks). 

I don't know about microC/OS, but the nios cpu doesn't have the required locked bus ops.
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