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Valued Contributor III
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OpenCores I2C No Output Signal

Hi guys, 

 

First off, I just started using FPGAs about a month ago, and am only just beginning to use Nios II, so suffice to say I am very new to this. 

 

I'm working with a DE0 Nano on project for which I am using the OpenCores I2C ported to the Avalon bus found on the AlteraWiki. I want to use it to communicate with an external IMU sensor board that I have. If you've successfully used this in the past, please have a quick read and see if you can help me out. 

 

I've used SOPC builder to design the system (see screenshot attached). 

 

This the code in Eclipse that I am using: 

 

#include <stdio.h># include "system.h"# include "altera_avalon_pio_regs.h"# include "i2c_opencores.h" int main() { printf("Hello from Nios II on steroids (SDRAM) !\n"); // initialise I2C Core at 100kHz I2C_init(I2C_0_BASE,ALT_CPU_FREQ,100000); return 0; } 

 

Turning on the debug flag returns the following: 

 

Hello from Nios II on steroids (SDRAM) ! Initializing I2C at 0x0, with clock speed 0x2faf080 and SCL speed 0x186a0 and prescale 0x63 

 

The base address is the same as the one in SOPC builder. 

 

When initialising I2C, I am assuming the clock signal should be observable using a logic analyser on the output pin, so I have assigned the signal to GPIO pin 33. However, the signal remains stuck at VCC. I don't know what is causing this error. I have tried mapping the signal to an LED and using a very low I2C clock frequency to see if it's stuck at VCC or if the initialisation has no effect at all, but the LED stays at GND. So my guess is that the problem lies in linking the I2C component with the output pins. 

 

If you could help me out it would be greatly appreciated. 

 

Thanks! 

 

PS: I don't whether this is of concern, but for some reason Quartus warns me during compilation that clk_50 hasn't been assigned as a clock.
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Valued Contributor III
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VCC is the expected state of both lines when you aren't doing anything on the I2C bus. Even the clock will only toggle when you are actually using the bus. Try to read or write something and see if the clock line toggles then.

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Valued Contributor III
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Hi Daixiwen, 

 

Thanks for the tip. I've been sending multiple signals after the I2C_INIT command, but the clock still fails to toggle (I sampled it using a Logic Analyser while it was supposed to be sending the signals) 

 

Neither SCL not SDA change. I really don't know what's going wrong and where. I suspect it might be resets, so I'll try adjusting those. If you have any more suggestions, do let me know! 

 

Thanks!
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Valued Contributor III
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Those problems are hard to debug. I suggest to use signaltap on the I2C component to check what is going on on your component. Check both the Avalom MM signals, to verify that the component is configured and controlled correctly, and the exported signals to monitor the I2C outputs.

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Valued Contributor III
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Hi! I know this thread is old, but I am having the same problem with the I2C_opencores IP core: both my scl and sda lines are stuck at high, as if nothing was happening.  

You dont happen by chance to remember what the problem was? 

I have never used signaltap before but after reading the thread I will try to give it a go. 

Any tips would be appreciated. :P
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Valued Contributor III
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NVM, I found this post: 

http://www.alteraforum.com/forum/showthread.php?t=39610 

 

I guess it is exactly the same problem so I will try it out.  

Cheers!
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Novice
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Hi, I'm facing the same problem with the I2C OpenCores IP v13.0: my SCL and SDA lines are stuck at VCC. Any tips would be appreciated, thanks in advance.

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