PCIe BAR mapping

[RVadl]

Background: Our system with Altera Cyclone IV FPGA requires 5 devices namely 3 Ethernet MACs and 2 HDLC channels on Cyclone IV FPGA. We are using a PCIe interface between FPGA and processor.

Queries:

1. We see that PCIe uses 3 out of the 6 BARs available, leaving only 3 BARs for devices. Is there any way to reduce the no.of BARs used by PCIe there by allowing more devices to get connected on PCIe?

2. Can we have more than one device on a single BAR with a different address map? If yes, can you share any literature available.

[Abe]

The PCIe BAR is a register space that you can use to map peripherals into the PCIe subsystem. Each PCIe bus can map upto 32 devices using the BAR. You have to calculate the memory address mapping requirement for each and map them accordingly to the BARs.

[anilinintel]

you can connect more than 1 device to any bar. I usually connect 4 devices to bar2 and i will start with 0x0 for the first device and i will maintain continuity till the last device. you can do this by editing <bar tab> in qsys design . you have to take one more caution here, if your vmap is 64MB from the host then all the devices u connect together together to any single bar should not exceed 64MB. ofcourse, if it is above that , u can use windowing in host appcode or HW windowing via address span extender. Hope this helps dude!!!