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Altera_Forum
Honored Contributor I
706 Views

PCIe Memory Write/Read abnormal behavior

We have a PCIe core that is configured as a rootport. It is connected  

to a switch which has a single device on the downstream side. We  

enumurated the PCIe busses successfuly and moved on to memory IO  

mapping. the device has 1MB memory and we configured its base address  

to 0x40000000. We set The command register to 6, enabling memory space  

and bus master. 

The downstream bridge, connected to the device, memory base/limit  

register is set to 0x40004000, so as the upstream bridge connected to  

the root-port. All have memory space and bus master enabled. 

 

Now we are facing 2 problems: 

1. We can write to/read from even addresses of double-words (0x00,  

0x08, 0x10, etc.), but when we read from odd DW addresses (e.g. 0x04,  

0x0c, etc.) we receive only the header of the TLP packet (indicating 1  

DW, 4 bytes) but no data is available on the FIFO. 

 

2. When we write memory with multiple words payload we read back old  

data, i.e. the memory write did not take place at all. 

 

 

PCIeFnWriteMemory32: requester_id 0000 (0,0,0), tag 1F, target_addr  

40000100 , data 123ABCDE 

TX Data = 0x40000001 

TX Data = 0x00001f0f 

TX Data = 0x40000100 

TX Data = 0x00000000 

TX Data = 0x123abcde 

TX Data = 0x00000000 

PCIeFnWriteMemory32: requester_id 0000 (0,0,0), tag 1F, target_addr  

40000104 , data 12ABCDEF 

TX Data = 0x40000001 

TX Data = 0x00001f0f 

TX Data = 0x40000104 

TX Data = 0x00000000 

TX Data = 0x12abcdef 

TX Data = 0x00000000 

PCIeFnReadMemory32: requester_id 0000 (0,0,0), tag 1F, target_addr 40000100 

TX Data = 0x00000001 

TX Data = 0x00001f0f 

TX Data = 0x40000100 

TX Data = 0x00000000 

 

RX Data = 0x4a000001 

RX Data = 0x09000004 

RX Data = 0x00001f00 

RX Data = 0x00000000 

RX Data = 0x123abcde 

RX Data = 0x123abcde 

completion status 0, Successful Completion (SC) 

PCIeFnReadMemory32: requester_id 0000 (0,0,0), tag 20, target_addr 40000104 

TX Data = 0x00000001 

TX Data = 0x0000200f 

TX Data = 0x40000104 

TX Data = 0x00000000 

 

RX Data = 0x4a000001 

RX Data = 0x09000004 

RX Data = 0x00002004 

RX Data = 0x00000000 

RX FIFO is empty !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! 

completion status 0, Successful Completion (SC) 

 

Has anyone encounter such behavior? Any ideas? 

 

S.
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1 Reply
Altera_Forum
Honored Contributor I
35 Views

Found the problem ! The TX packet has two extra DW of 0x00000000 which must not be there. This violates the memory write spec. for 32bit access. So, instead 

of: 

TX Data = 0x40000001 

TX Data = 0x00001f0f 

TX Data = 0x40000100 

TX Data = 0x00000000 

TX Data = 0x123abcde 

TX Data = 0x00000000 

 

it should be: 

 

TX Data = 0x40000001 

TX Data = 0x00001f0f 

TX Data = 0x40000100 

TX Data = 0x123abcde 

 

The SW guy has a red face now... 

 

S. (HW guy)
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