Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12435 Discussions

PCIe RootPort+EndPoint Simulation

Altera_Forum
Honored Contributor II
933 Views

I have designed two systems - a RootPort and an EndPoint on two different PCBs, each with a NIOS II. Now, I am trying to do system-level simulation with both designs in one testbench. 

My Endpoint design does not use a DMA in the normal sense. I managed to simulate the RooPoint example fine, but trying to adapt it to my requirement proved very difficult making it useless. 

The test driver is very difficult to follow because it uses the PIPE access and is not general purpose enough. 

I would like to do the RP and EP configuration using the PIPE method using two actual designs and the rest via the pcie_rx and pcie_tx wires. 

Has anyone done system-level simulation with two real design (not BFM + real)? 

 

P.S. The RP works fine in HW while the EP only responds to enumeration but not memory write/read TLP. 

 

S.
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
90 Views

how did you get altera bfm driver with root port configuration? i don't have testbech folder under my root_port folder.

Altera_Forum
Honored Contributor II
90 Views

When you generate the SOC in QSYS you can add a BFM master. When you synthesize the SOC the BFM drops out. If you have a NIOS II you can hold it in reset by using a "force" command in you testbench. This is so it does not interfere with your simulation.

Reply