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ArthurDent
Beginner
1,397 Views

PHY MDIO physical base address on Cyclone V SoC

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Hi

I am working on interfacing a second PHY which is connected to one of the HPS EMAC using FPGA IOs, but I have some MDIO issues on my Cyclone V SoC board. The PHY responds correctly on the MDIO interface (checked with Signaltap) but the linux driver only reads zeros.

To do some simple debugging I want to use memtool to access the MDIO interface. According to https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/soluti...

this should be straight forward:

“Read access from an external PHY can be done using the MDIO interface as follows:

  • Perform an Avalon-MM master write to the MDIO core registers at address offset 0x21, specifying the external PHY device address (MDIO_DEVAD), port-address (MDIO_PRTAD) and register address (MDIO_REGAD).
  • Issue an Avalon-MM master read of the 32-bit MDIO_ACCESS register at offset 0x20. "

 

However, I am missing a key parameter: What is the base address for MDIO access?

E.g. emac0 and emac1 are mapped to base address 0xFF700000 and 0xFF702000, but I can't find any information about MDIO.

 

Anyone who can help me out?

 

BR

AD

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Fawaz_J_Intel
Employee
152 Views

Hello sir,

The MDIO can be accessed via GMII_Data & GMII_Address.

Please refer to the TRM:

https://www.intel.com.br/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_54001.pd...

 

 

GMII_Address on page 18-151

The GMII Address register controls the management cycles to the external PHY through the management interface. The offset is 0x10.

 

GMII_Data on page 18-154

The GMII Data register stores Write data to be written to the PHY register located at the address specified in Register 4 (GMII Address Register). This register also stores the Read data from the PHY register located at the address specified by Register 4. The offset is 0x14.

 

 

Hope this might help

 

Thanks

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Fawaz_J_Intel
Employee
153 Views

Hello sir,

The MDIO can be accessed via GMII_Data & GMII_Address.

Please refer to the TRM:

https://www.intel.com.br/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_54001.pd...

 

 

GMII_Address on page 18-151

The GMII Address register controls the management cycles to the external PHY through the management interface. The offset is 0x10.

 

GMII_Data on page 18-154

The GMII Data register stores Write data to be written to the PHY register located at the address specified in Register 4 (GMII Address Register). This register also stores the Read data from the PHY register located at the address specified by Register 4. The offset is 0x14.

 

 

Hope this might help

 

Thanks

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