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PIO interrupts on Cyclone SoC

Altera_Forum
Honored Contributor II
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Hi all 

I hope someone can point me in the correct direction regarding PIO interrupts. 

I have been playing around with the GHRD design trying to figure out how the PIO interrupts are mapped/connected to the linux system: 

 

From the original GHRD design there is a dipsw_pio module with IRQ=0 connected to f2h_irq0 on HPS. 

The input pin on the dipsw_pio is connected to a button so I can easily generate an interrupt. 

 

When I enable the dipsw_pio irq mask (DIPSW_PIO_BASE+8) = 1, this line pops up in “/proc/interrupts” : 

35: 0 altera-gpio 0 Edge 

Pushing my “irq-button” I can see the “irq 35” counts up correctly, i.e. working as it should. 

 

Problem 1: 

Why irq 35? I have tried various QSYS irq mapping for the DISPSW_PIO with corresponding device tree files. 

Currently my DISPSW_PIO is connected to IRQ=17 on f2h_irq1. My dtb/dts file: 

dipsw_pio: gpio@0x100040800 { 

compatible = "altr,pio-16.0", "altr,pio-1.0"; 

reg = <0x00000001 0x00040800 0x00000010>; 

interrupt-parent = <&hps_0_arm_gic_0>; 

interrupts = <0 89 1>; 

clocks = <&clk_0>; 

altr,gpio-bank-width = <4>; /* embeddedsw.dts.params.altr,gpio-bank-width type NUMBER */ 

altr,interrupt-type = <1>; /* embeddedsw.dts.params.altr,interrupt-type type NUMBER */ 

altr,interrupt_type = <1>; /* embeddedsw.dts.params.altr,interrupt_type type NUMBER */ 

edge_type = <0>; /* embeddedsw.dts.params.edge_type type NUMBER */ 

level_trigger = <0>; /* embeddedsw.dts.params.level_trigger type NUMBER */ 

resetvalue = <0>; /* embeddedsw.dts.params.resetvalue type NUMBER */ 

# gpio-cells = <2>; 

gpio-controller; 

}; //end gpio@0x100040800 (dipsw_pio) 

 

I have tried with various irq settings, but this does not seem to make any difference, it always pops up as “irq 35” when I enable dipsw_pio irq mask (DIPSW_PIO_BASE+8) = 1 

Can anyone share some insight here? 

 

Problem 2: 

I have then mapped in another PIO module (identical to dipsw_pio) with a different input button to generate irqs. 

pio_test: gpio@0x100040900 { 

compatible = "altr,pio-16.0", "altr,pio-1.0"; 

reg = <0x00000001 0x00040900 0x00000010>; 

interrupt-parent = <&hps_0_arm_gic_0>; 

interrupts = <0 43 1>; 

clocks = <&clk_0>; 

altr,gpio-bank-width = <1>; /* embeddedsw.dts.params.altr,gpio-bank-width type NUMBER */ 

altr,interrupt-type = <1>; /* embeddedsw.dts.params.altr,interrupt-type type NUMBER */ 

altr,interrupt_type = <1>; /* embeddedsw.dts.params.altr,interrupt_type type NUMBER */ 

edge_type = <0>; /* embeddedsw.dts.params.edge_type type NUMBER */ 

level_trigger = <0>; /* embeddedsw.dts.params.level_trigger type NUMBER */ 

resetvalue = <0>; /* embeddedsw.dts.params.resetvalue type NUMBER */ 

# gpio-cells = <2>; 

gpio-controller; 

}; //end gpio@0x100040900 (pio_test)  

 

Enabling pio interrupt mask for both: 

pio irq mask (DIPSW_PIO_BASE+8) = 1 

pio irq mask (PIO_TEST_BASE+8) = 1 

 

I get this two lines in “/proc/interrupts” : 

36: 3 altera-gpio 0 Edge 

68: 5 altera-gpio 0 Edge 

Both IRQ works, but the one which previous was numbered 35 is now 36 (why?), and the new one is 68… 

 

Problem 3: 

I want to use the ko-driver based on the fpga_uinput.c example from github, but this can be a problem since I do not understand how my PIO irqs are mapped in the linux system. 

In the fpga_uninput.c example one need to specify the IRQ number:# define UINPUT_INT_NUM <?> 

However: 

If I first enable the PIO mask and check/proc/interrupts to get the IRQ number and use this number to compile my fpga_uinput.ko. E.g. :# define UINPUT_INT_NUM 68 

Then my ko-driver seems to work, but there should be possible to know how the irqs are mapped based on the dts file???? 

 

Platform: 

DE0-Nano-SoC 

GHRD 16.1 (modified and rebuilded for DE0-Nano-SoC) 

Linux RT: Linux cyclone5 4.1.22-ltsi PREEMPT RT 

 

Regards, 

ArthurDent
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