PLL jitter warning

[Altera_Forum]

I have a custom Cyclone/NiosII board and the NiosII 5.0 toolset. 

 The design file has 2 PLL instances: 1) 'cpu_pll' takes 33Mhz input on inclk0 pin and outputs 50mhz on c0 pin for nios core. 2) 'sdram_pll' takes 33Mhz input on inclk0 pin and outputs 50mhz with phase shift on c0 pin for external sdram.  Compiling this project under 5.0 results in just one PLL being used, but always  generates a warning about jitter for the 2nd PLL output. The board  works, but I'd like a clean compile.  I tried using one PLL instance to supply both 50Mhz clocks with the core output on c0, and the phase shifted sdram output on e0. The fitter fails  claiming some PLL resources it needs are already in use.  Next I tried two different PLL instances, but using the e0 output for the sdram  PLL. This time the failure is "cant use the same input for two PLLs".  What is the correct way to do this??

[Altera_Forum]

All that warning means is that c0 is compensated so all others with not be as clean essentially. If you moved the compensation to c1 you would get this warning for c0 instead. A PLL is fed by a dedicated circuit so if you try to route that clock to the other side of the FPGA the tools will tell you this (you wouldn't want to do that anyway). 

 Having the 50MHz "main" clock and the 50MHz shifted clock coming from the same PLL is exactly what you want to do. Also at 50Mhz you really don't have to worry about jitter (if you were barely passing timing that's a different story though). I recommend you look at the device datasheet and study it's clock network so you know what each PLL can input and output. Judging by the description of the error you get sharing the PLL, you need to take a look at a Nios II Cyclone reference design since I think you are using the same clock pins (one PLL feeds the other in that design using a board trace).

[Altera_Forum]

'Having the 50MHz "main" clock and the 50MHz shifted clock coming from the same PLL is exactly what you want to do. ' 

 I thought so, but the refererence design does not do this, and it does not show using the same PLL to provide two different phase shifts. Looking at the Cyclone device handbook shows my dilemma. My main clock comes in on CLK0 (PLL1), but my sdram is fed by the PLL2 output. Without cuts and jumpers, it looks like I am stuck using both PLLs. How is the synthesis able to eliminate one of the PLLs without breaking the rules spelled out in the handbook?