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Valued Contributor III
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Parallel Flash memory access failed

Hello, 

 

I am designing a simple system with a 4CE40 and a Spansion flash memory (S29GL512 : 64MB in 16bits organisation). But when I make a "hello world" software, it fails at "checking" step. Here are some more details : 

 

HARDWARE :  

- I use Quartus 11.0 toolkit. 

- the board is designed by me. The FPGA owns a NIOSII/e system with a tristate bridge and the CFI flash memory interface. Nothing else. 

- I checked the FPGA/memory connections, power supply etc ... => all OK 

- Nothing special during synthesys process, everything looks good. 

 

SOFTWARE : 

- I built a hello world project with Eclipse rev Helios Service Release 1 

Build id: 20100917-0705. 

- I launch my soft with NiosII shell window using this command : 

bash-3.1$ nios2-download -g hello.elf && nios2-terminal 

 

- I get this answer : 

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 

Pausing target processor: OK 

Initializing CPU cache (if present) 

OK 

Downloaded 29KB in 0.4s (72.5KB/s) 

Verifying 00001020 ( 0%) 

Verify failed between address 0x1020 and 0x122B 

Leaving target processor paused 

bash-3.1$ 

 

I think that the board has no problem (I tested each electrical connection between the FPGA and the flash). I tryed the same software with internal memory and it worked. There is a problem with the flash but I don't know where (SOPC system ? Compiler options ? ...) 

 

Please could anybody help me to anderstand ? 

 

Cyril
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Valued Contributor III
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Are you trying to write to flash memory with the JTAG debugger?? 

That won't work. 

Neither can you use it for program data.
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Valued Contributor III
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Hi dsl, 

 

Thx for answering. 

 

Actually, there is a JTAG-UART in the system. It worked when I tryed the soft with internal memory. 

How am I supposed to proceed "normally" to write to the memory ?
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Valued Contributor III
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Flash memory is effectively read-only memory that can be written to by very specific bus cycle sequences. 

The memory datasheet will tell you how to write to it, and you might find some standard software that can do it. 

I'm also not sure how easy it is to perform the desired cycles through the normal bus width adapter that gets added between the 32bit Avalon bus and a 16bit memory. 

You can execute code from the flash (and have the cpu's reset vector addressing it), but you'll need other memory for data and stack and for the code running while you do the flash erases and writes.
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Valued Contributor III
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Ok, I understand. 

I just tried to add embeded RAM memory in SOPC. 

The pb is the same... 

 

I compared my design with a tutorial issued from DE1 Altera dev board. They use a 8bit data bus for their flash memory. But the components used in both SOPC designs are likely the same : NIOSII/e, tristated bridge, flash memory interface. But the flash interface versions looks different ... 

 

Can't CFI module program an external // flash memory ?? Do I need to use another specific tool to download my program in the flash device ? 

 

Thank you for your help !
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Valued Contributor III
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Please, anybody could help me ?

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Valued Contributor III
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Hello cyrill.garric, 

 

I have the same problem. But only with quartus 10.1SP1.  

 

I used timing setup: 100ns wait 200ns hold 100ns. 

 

No good result: 

Using cable "USB-Blaster ", device 1, instance 0x00 Resetting and pausing target processor: OK No CFI table found at address 0x00000000 Original contents (after writing 0xF0 and 0xFF to address 0x00000000): 0: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 10: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 20: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 30: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 40: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ Contents after writing 0x98 to address 0x000000AA: Same after writing 0x0098 to address 0x00000154: Same after writing 0x00000098 to address 0x000002A8: Same after writing 0x98 to address 0x00000055: Same after writing 0x0098 to address 0x000000AA: Same after writing 0x00000098 to address 0x00000154: Same after writing 0x98 to address 0x00000154: Same after writing 0x0098 to address 0x000002A8: Same after writing 0x00000098 to address 0x00000550: 0: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 10: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 20: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 30: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ 40: A8 09 00 04 A8 09 00 04 A8 09 00 04 A8 09 00 04 ................ Ignored possible autoselect code A8-A8 as no override data present in section Ignored possible autoselect code 09A8-09A8 as no override data present in section Leaving target processor paused  

 

What timing to you use? And is it working now? 

 

Thanks
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Valued Contributor III
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Hi Neptunus, 

 

Actually, the flash device was dead. That was the root cause of my problem. 

After changing the device, my design worked normally. Here are the timings I used : 

Setup : 80ns 

Wait : 160ns 

Hold : 80ns 

 

But that timings depend on the flash device itself. In case you have a doubt, please have a look on its datasheet timings. 

 

Regards, 

Cyril
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Valued Contributor III
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--- Quote Start ---  

Hi Neptunus, 

 

Actually, the flash device was dead. That was the root cause of my problem. 

 

 

--- Quote End ---  

 

 

Hi Cyril, 

 

How did you end up programming your flash memory after you replaced the chip? 

 

Did you use the Flash Programmer that comes with Eclipse, or another method? 

 

Thanks.
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Valued Contributor III
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Hi fheineman, 

 

I used the Altera program to test memories. I loaded the program to embeded RAM memory and simply runed it from Eclipse. 

 

But I guess I could also have used Flash Programmer. 

 

Cyril
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Valued Contributor III
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hi cyril 

 

Are you finished the project and working well with the flash? 

May you post the Qsys connections design!?
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Valued Contributor III
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--- Quote Start ---  

 

 

Are you finished the project and working well with the flash? 

May you post the Qsys connections design!? 

--- Quote End ---  

 

 

Hello haulisson, 

 

Welcome to the forum. I attached two Qsys designs for the Nios II Embedded Evaluation Kit, Cyclone III Edition (NEEK). One is with sdram and flash memory, each having its owm address and data buses. The other is with ssram and flash memory, both sharing the same address and data buses

 

The generic tristate controller component for the external Flash memory needs to be configured for the specific Flash memory device in your system. Likewise, the pin sharer component used in the latter example needs to be configured for your design.
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Valued Contributor III
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Thx fheineman, I'm very grateful. 

 

Could you show the configuration that you used in the signal timing TAG at Generic Tri-State Controller?
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Valued Contributor III
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--- Quote Start ---  

I attached two Qsys designs for the Nios II Embedded Evaluation Kit, Cyclone III Edition (NEEK). One is with SDRAM and Flash memory, each having its owm address and data buses. The other is with SSRAM and Flash memory, both sharing the same address and data buses. 

 

--- Quote End ---  

 

Can u attach whole Qsys design containing SDRAM and flash?? i want to know timing properties for the SDRAM,so if it is possible for you to place your design project instead of just screenshot? 

Is it working well? Have you tested on NEEK board? If yes then please attach design for SDRAM and flash here.I think this can be very useful for others.
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Valued Contributor III
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Hi everybody, 

 

Sorry, but my board is beeing redesigned, so I have been working on something else. It will embed 2 SDRAM and a parallel flash sharing the same address and data bus. Designing a DDRAM board was a little bit too tricky for me :oops: 

 

If it works, I'll post the design (in SOPC Builder). 

Cyril
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Valued Contributor III
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--- Quote Start ---  

Can u attach whole Qsys design containing SDRAM and flash?? i want to know timing properties for the SDRAM,so if it is possible for you to place your design project instead of just screenshot? 

Is it working well? Have you tested on NEEK board? If yes then please attach design for SDRAM and flash here.I think this can be very useful for others. 

--- Quote End ---  

 

 

I attached a zip file containing the three Qsys files for this project. I am trying to find a way to upload the entire Quartus II project, but it is too large for this forum (57 MB). I will upload the project files to Altera Wiki and create a page there with all the details. 

 

Meanwhile you can open these files in Qsys to view the various connections and component configurations.
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Valued Contributor III
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I attached the BSF file that I used for the top level of my Quartus II project. This may give you more insight as to how the SSRAM and Flash memories are connected in the system.

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Valued Contributor III
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--- Quote Start ---  

I attached a zip file containing the three Qsys files for this project. I am trying to find a way to upload the entire Quartus II project, but it is too large for this forum (57 M. I will upload the project files to Altera Wiki and create a page there with all the details. 

 

Meanwhile you can open these files in Qsys to view the various connections and component configurations. 

--- Quote End ---  

 

 

Thanks for the qsys files,but it is SSRAM+Flash,and i wanted to see sdram+flash,very simple simple qsys design as u depicted in screenshot (Nios II + sysid+sdram+flash+tristate bridge). 

 

I think with only these many components,design wont be too large and before making a .zip file,u can delete "db and incremental db and unnecessary files(like .rpt and .smsg)" then make a zip file and post ur project.
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Valued Contributor III
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--- Quote Start ---  

Thanks for the qsys files,but it is SSRAM+Flash,and i wanted to see sdram+flash,very simple simple qsys design as u depicted in screenshot (Nios II + sysid+sdram+flash+tristate bridge). 

 

 

--- Quote End ---  

 

 

Please see the attached zip file containing a reference design for Cyclone III NEEK that uses sdram + external flash memory + triple speed ethernet components. This design should work on the NEEK without modification.  

 

Just download the zip file and extract to your C: drive root directory. Double-click on the niosii_ethernet_standard_3c25.qpf file to launch the Quartus II design. Open the Programmer within Quartus and change the file to the niosii_ethernet_standard_3c25.sof (it may be pointing to a different directory that does not exist). Program the NEEK, then launch the Nios II SBT for Eclipse to create software. 

 

I suggest creating an app based on the Memory Test example software to test the Flash memory. 

 

If you are really bold, you can download the Simple Socket Server Design Example located at: 

http://www.altera.com/support/examples/nios2/exm-hello_world.html 

 

You must follow the instructions very carefully to get the SSS example to work, but with the proper finesse, it will work on the NEEK with the attached hardware design. 

 

Good luck, and have fun with this...
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Valued Contributor III
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Here is the file again. I'm not sure the attachment worked on my previous post...

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