Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
2,668 Views

Pausing target processor: not responding.

when i try to run as NIOS II hardware, i am getting this error, 

 

 

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 

Pausing target processor: not responding. 

Resetting and trying again: FAILED 

Leaving target processor paused 

 

 

how can i correct it, 

Its running in the simulator though (NIOS instruction set simulator)
0 Kudos
17 Replies
Altera_Forum
Honored Contributor I
498 Views

The compilation msgs shown are, as in attached file , it shows timing reqs not met

Altera_Forum
Honored Contributor I
498 Views

It is possible that your processor is held in reset at the firmware level. Make sure your processor has a valid clock and that the reset polarity is correct.

Altera_Forum
Honored Contributor I
498 Views

I agree with kosh271 

Check resets connection (in top level, a lot of times the problem is there).
Altera_Forum
Honored Contributor I
498 Views

I used the example came with the De2 115 board 

I am new to fpga , can you help me in sort out , where can i change the clock and reset ? 

 

 

I attached a screen shot of my configurations
Altera_Forum
Honored Contributor I
498 Views

kindly someone assist me

Altera_Forum
Honored Contributor I
498 Views

The compilation messages indicate that you don't have the license for the Nios CPU. This means Quartus generates a time limited .sof file for evaluation purposes. When you configure the FPGA you will see an OpenCore window saying you are in evaluation mode. Do not close this window or the Nios CPU will stop working and you can get this "non responding" error.

Altera_Forum
Honored Contributor I
498 Views

yes , i didnt closed the window , then also the same problem persists

Altera_Forum
Honored Contributor I
498 Views

Did you modify the example in any way? Check epsecially the clock and reset input. The reset is active low so it must be high for the system to work. You can verify that the clock is running by using signaltap, either by monitoring the clock signal itself, or by using it as the clock in signaltap (it will say "waiting for clock" if the clock isn't toggling).

Altera_Forum
Honored Contributor I
498 Views

what these lines show ? 

 

 

Warning (10034): Output port "LEDR" at myfirst_niosii.v(44) has no driver 

Warning (10034): Output port "FL_ADDR" at myfirst_niosii.v(47) has no driver 

Warning (10034): Output port "FL_CE_N" at myfirst_niosii.v(48) has no driver 

Warning (10034): Output port "FL_OE_N" at myfirst_niosii.v(50) has no driver 

Warning (10034): Output port "FL_RST_N" at myfirst_niosii.v(51) has no driver 

Warning (10034): Output port "FL_WE_N" at myfirst_niosii.v(53) has no driver 

Warning (10034): Output port "FL_WP_N" at myfirst_niosii.v(54) has no driver
Altera_Forum
Honored Contributor I
498 Views

It means that you defined some output ports on your top level verilog file that you didn't connect to anything inside your design.

Altera_Forum
Honored Contributor I
498 Views

hello, 

 

i am currently working on DE2 70 altera kit for my final year project and want to send messages using ethernet port. i am working using SOPC builder. Firstly i want to run a small program(eg. LEDs). i have created a NIOS II system using SOPC builder, then i have used altera monitor program to compile a c program.  

system got downloaded on to the board but when i m trying to load it i am getting the following error. 

 

 

Usingcable "USB-Blaster [USB-0]", device1,instance 0x00 

Pausingtargetprocessor: not responding. 

Resetting and trying again: FAILED 

Leavingtargetprocessorpaused 

 

 

please kindly help me to sort this error.
Altera_Forum
Honored Contributor I
498 Views

Did you chech the clock and reset signals, as already suggested in the thread?

Altera_Forum
Honored Contributor I
498 Views

i have assigned the clock and reset to iCLK_50 and iKEY(0) in the pin assignment vhdl file. but still it doest work. arent they correct?

Altera_Forum
Honored Contributor I
498 Views

Can you check the polarity of your reset signal? The reset input on an SOPC/QSYS design is active low, so it needs to be '1' for the CPU to work. I don't know the polarity of the KEY signals on the DE2 board.

Altera_Forum
Honored Contributor I
498 Views

I had some problems with the board, 

 

now got response from the board
Altera_Forum
Honored Contributor I
498 Views

I had a similar problem that was solved by making sure the NIOS reset output (jtag_debug_module_reset) is connected to the reset inputs of the other components, including the NIOS itself (reset_n). The loading process was unable to pause the processor until this change was made.

Altera_Forum
Honored Contributor I
498 Views

I too got similar error and resolved it by making sure that my Clock and Reset pins at the top level were correctly assigned (Pin Planner/ Assignment Editor). Once fixed, this resolved the problem.  

 

So it appears, for such messages, one must look closely at the top level (including Nios / Connected components) Clock and Reset connections.