Hello,I'm using NIOSII software development tool version 10.0 SP1. I'm using sopcinfo file built in version 10.0 sp1. During compilation of my software I receive the following error: unable to reach oscpuusage (at 0x0050e2cc) from the global pointer (at 0x000bf430) because the offset (4517532) is out of the allowed range, -32678 to 32767.
The memory device is located within address space of 28bit. Also, compilation in version 9.1 sp1 with the same sopcinfo file is built with no problem at all! What might be the problem? Thanks, ITCO
The variable 'OSCPUUsage' is being assumed to be in the 'small data' segment when treated as an 'extern', but the actual definition is 'normal' data.This might have happened because, for some reason best known to themselves, the default location for 4-byte 'external' data items was changed from 'small' to 'normal' between the gcc3 and gcc4 builds. Possibly the definition and use were compiled with different versions of gcc. Of course, for any performance. you need as much data as possible in the 'small data' segment. The gcc4 compiler build (from Altera) also unconditionally puts any switch statement jump tables into '.code' (instead of '.rodata). This is also rather sub-optimal for systems running with tightly-coupled code and data. (It is, according to the comments, needed for PIC code for shared libraries! no need to foist it on all of us.)
Hi,Solution has been found: Following DSL post reply, there is actual difference of NIOSII EDT between version 9.1sp1 and 10.0sp1 (they use different GCC versions). Therefore, I've build new BSP and Application based on "hello_ucosii" project, and added my code to its folder. Of-course I've had to reconfigure the BSP and the application manually, but it works. Thanks, ITCO
Yes, except that the gcc4 versions will execute slower because the data is no longer in the 'small' data area and thus not accessible by a single instruction. Instead the address must be calculated and a register used, although this probably only adds one instruction, gcc tends to cache the address in a register leading to additional register pressure and register spills to stack.