Does anybody have an experience or knowledge how to realize physical separation of cores inside an FPGA?The location of the particular core (e.g. a crypto core) can be constrained but how to verify the bitstream that there are no signals coming to/from the core except the port connections specified in the RTL design? I'm aware of moats idea and limited use of routing resources but the question of bitstream verification still remains unaswered. Any suggestions?
it sounds like you might want to use the red/black separation feature available in Cyclone III LS, but you'll have to contact an Altera distributor to get a license for it