Hi,I would like to implement a SGDMA (stream-to-memory) to store blocks of sampled data in internal memory for signal processing. The implementation should be a PING-PONG-Buffer, so that one block can be processed while the other one is being filled again. I managed to implement two descriptors which are linked so that the first one points to the second one and vice versa. This works fine. However, the problem is, how can I verify which of the two buffers causes the interrupt? From the register maps I can't see any difference and the next_descriptor_pointer always shows 0x0. I'm afraid I loose synchronization in case I miss one IRQ. Has anybody an idea how to ensure the full buffer is being processed? Thanks and regards Michael
It's been a while since I have used that DMA after looking at the documenation it appears that there is a bit in the control register (not the descriptor) that you can set to have the DMA interrupt after every descriptor is completed. So in your ISR you would have to keep track of which descriptor completed.In your linked list you would have to make sure the DMA doesn't move to the next descriptor automatically otherwise whatever else in your system is working on the buffer might not be done with it yet. So I'm assuming you don't set the owned by hardware bit at the end of your linked list and wait for the DMA to complete first right? (otherwise I think you have a bigger syncornization problem to think about). Have you seen my DMA yet? It might be a lot easier to use for what you are trying to do: http://www.alterawiki.com/wiki/modular_sgdma I'm debugging an issue in it where if one packet starts the clock cycle after the previous one completed then the first address is not written to, but other than that it works pretty good.
Dear BadOmenthanks for the quick reply. I configured the DMA to get an IRQ after each descriptor completed, but the problem is, that I cannot find out in the ISR which descriptor caused the IRQ. I set the owned by HW bit and configured the DMA not to clear it (PARK bit set). You suggested to change this and manually restart the DMA in the ISR. But what if data arrives from the streaming interface before the ISR has restarted the DMA? Wouldn't this mean that data will be lost? Thanks Michael
That's correct, if data arrives while the DMA is idle then it won't accept the new data. That said, if you are dependent on the DMA always being ready then that tells me you need some buffering in your system. Typically you would have a FIFO in the data path before the DMA so that you can handle cases like these. For example if the SGDMA and some other master were accessing the same memory, the DMA might be starved for cycles, it's internal FIFO becomes, and then it stops accepting data.