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Altera_Forum
Honored Contributor I
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Pipelined SRAM

Having trouble interfacing CY7C1470 pipelined SRAM to nios. It does not seem like a combination of signal timing parameters in the Generic Tri-state Controller exists that can create the staggered write cycle that this chip needs. I have inserted delays in a test bench that proves that delays are needed, but inserting logic past the tri-state drivers in real life is not an option. Am I missing something? :confused:

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