Please help me ......SDRAM DE2

[Altera_Forum]

:( i have a problem.....my project need to use sdram on de2 board altera...but i dont know to use sdram......some master help me.... 

i use sopc to configure a sdram controler on my system...... but i dont know to program c to access it.....i mean to read or write on sdram through sdram interface or anything.... thank so much......

[Altera_Forum]

Read literature. Use DMA or SGDMA for memory transfers. Check alterawiki.com for examples.

[Altera_Forum]

My best advice is to take a look at DE2 examples. 

Anyways, it depends a lot on how do you want to access the DDR: - do you want to read/write it from a custom IP/design you are developing or do you want to access it from a NIOS softcore?  In the case of NIOS things might be easier, you just need to add the SDRAM controller to the SoPC and map to NIOS memory space. In the case of a custom IP core, it depends a lot on the design. My best advice would be to develop your IP core as an Avalon MemoryMapped Master, and take advantage of the Avalon bus infrastructure to use the sdram controller. DMA is not mandatory, and I would suggest to introduce it later and start with a simple design, maybe just a NIOS processor, the SDRAM and a PIO for leds.  Just another advice: rember that, in order to let the SDRAM work correctly, you must use a PLL which anticipates the phase of the clock going to the sdram in order to compensate transmission delays. So considering, for instance, that you want to run your design @ 100 MHz, you must introduce a PLL which outputs two clocks: - c0, 100 MHz, Ph: 0 degrees: the clock that you will use INSIDE the FPGA and that will clock the cpu, the SDRAM controller, and the other SoPC peripherals - c1, 100 MHz, Ph: -65°: the (anticipated) clock that you will output to the DRAM_CLK pin (be aware not to connect to anything inside the design, just to the output pin)  Anyway the best advice is to read getting started manuals inside the DE2 CDrom  Regards, Primiano

[Altera_Forum]

Thank you, primiato and socrates.......i think i was success building my system with sopc buider and i allso use PLL to create dependen clock for sdram controler block.... 

but i mean how can i use languge c to access into sdram controler....... i saw all examlple use verilog HDL to do that......anđ as primiato said to me that  "do you want to read/write it from a custom ip/design you are developing or do you want to access it from a nios softcore?"  so i think i want to access it from a custom IP.....because of your advice:-P if you dont mind you can teach to me about "custom ip/design"... i really need that because :cry:my project have to finish last month...  thank evey body so much......

[Altera_Forum]

Mmm there is some confusion here: you first state that you want to access SDRAM memory using C, but later you state you want to access from a custom IP. 

 I will try to be more clear, what you need to do is:  A) Interface a VHDL/Verilog hardware module you have developed to a SDRAM memory?  B) Develop software in C code just like you would do in any microcontroller/microprocessor and take advantage of SDRAM as main program memory?

[Altera_Forum]

oh....sorry primiano because im areal beginer....i think i want to create an aplication on my system.....and purpose of it that access into sdram...to read or write data on it.....so can you help me?:cry: 

but....i dont understand your question... "interface a vhdl/verilog hardware module you have developed to a sdram memory?" i just sturdy about creating an embedded system by Quatus II(use sopc builder), and than write an aplication on it.....and than my teacher asked to me building a system include nios2, memory on chip, jtack uart and sdram controler....than write a nios2 c-language program that write data to sdram chip and reads this data into registers... i have read alot of document......but i dont looking for any thing like that...  i hope you can help me.....thank so much....

[Altera_Forum]

So it seems that you do NOT have a custom IP core, but want to use Altera IP cores and then just write software. 

You do not have to bother in realizing a SDRAM controller, it is already provided by Altera. You just need to istantiate it in the SoPC builder and then connect it to i/o pins. My best advice is to take a look to the NIOS examples on the altera website or on the developement board cd, and get started with a simple SoPC system which has a NIOS core, a sdram controller and some PIO. After you succesfully build a NIOS SoPC, you can write your C software using the Eclipse software build tools for NIOS (which is distributed for free by Altera, https://www.altera.com/download/software/nios-ii/11.0)  Regards, Primiano

[Altera_Forum]

Thank so much, primiano....please help me one more times..... 

i have read "altera funtion library"...but i dont understand how to set up sdram driver and where is de2sdramdriver() macro... summary, it is: "in order to use the sdram, you must first set up the driver by:  - initialize the flash memory driver by calling the de2sdramdriver()macro.  - pass a pointer of type de2sdram to the macro as a parameter." Holping you reply !!!  nphung

[Altera_Forum]

You finish your project, the SDRAM work !? 

I am having the same problem many people on this forum seem to have had, but I have had no luck getting it to work.  SDRAM ref : Zetel a3v64s40etp g6  

[Altera_Forum]

when i know my problem ....i really thank for helping from primiano..... 

you can see his advise for me.....and think clearly about that.....it very usefull.....

[Altera_Forum]

system: 

De0 - SDRAM (A3V64S40ETP G6);  Quartus II 11sp1;  QSYS;  Nios II EDS (eclipse).   The lack of parameterization in the memories is a common flaw found in the Terasic kits. The realization of this is visible when looking up the forum for answers from Altera.   I'm trying to implement a simple Nios II SDRAM to have a little more memory.  I tried with the parameters of the "Embedded Peripherals IP User Guide", but nothing works. The frequency used in PLL as setting 50 MHz (20 ns) because Tac = 17ns.   I tried to set it to 100MHz (Ph-3rd) according to the datasheet "A3V64S40ETP G6", but has problems of ELF. I found many settings that were placed without concern for a frequency of operation and specification of memory.   So, I would like the configuration parameters of the SDRAM.  SERENETY NOW!!!!

[Altera_Forum]

Recently I have came upon these issues you are facing, and believe I can be of some help: 

 1. Follow this tutorial to integrate the SDRAM memory controller to your NIOS II processor: "Using the SDRAM Memory on Altera’s DE2 Board" (just google it, I can't provide you the link)  2. The SDRAM CLK must have a 3 ns phase delay from the Avalon interface clock. Besides using a PLL with a "-3 ns" delayed output, you must define time constraints accordingly.  3. You can read/write from/to the SDRAM using simple I/O macros, such as:  int val=123; IOWR( SDRAM_BASE, SOME_OFFSET, val ); val = IORD( SDRAM_BASE, SOME_OFFSET);  4. It is also possible to declare variables in the SDRAM because it is memory mapped, just like the internal SRAM memory. I haven't done that yet, but I have read it from a pdf file I found on google.  5. Something I noticed when I was testing the SDRAM is that there are some memory positions at the beginning and at the end of the memory that don't work properly (at least in my DE2 board). So I only use the following range of addresses: SDRAM_BASE+2048B < range < SDRAM_BASE+8MB-2048B As you can see I'm only throwing away 2KB (0.025%)... I was able to successfully write to all other memory positions.   Best Regards, Thomas.