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Altera_Forum
Honored Contributor I
1,193 Views

Porting DE_NET2 to NIOSII running on Quartus 12.1sp1 and QSYS

Hi, 

I'm trying to port DE_NET2 to Quartus 12.1sp1 and QSYS. 

I have created in QSYS dm9000a component based on DM9000A_IF.v file. The code: 

module DM9000A_IF( // HOST Side iDATA, oDATA, iCMD, iRD_N, iWR_N, iCS_N, iRST_N, iCLK, iOSC_50, oINT, // DM9000A Side ENET_DATA, ENET_CMD, ENET_RD_N, ENET_WR_N, ENET_CS_N, ENET_RST_N, ENET_INT, ENET_CLK ); // HOST Side input iDATA; input iCMD; input iRD_N; input iWR_N; input iCS_N; input iRST_N; input iCLK; input iOSC_50; output oDATA; output oINT; // DM9000A Side inout ENET_DATA; output ENET_CMD; output ENET_RD_N; output ENET_WR_N; output ENET_CS_N; output ENET_RST_N; output ENET_CLK; input ENET_INT; reg TMP_DATA; reg ENET_CMD; reg ENET_RD_N; reg ENET_WR_N; reg ENET_CS_N; reg ENET_CLK; reg oDATA; reg oINT; assign ENET_DATA = ENET_WR_N ? 16'hzzzz : TMP_DATA; always@(posedge iCLK or negedge iRST_N) begin if(!iRST_N) begin TMP_DATA <= 0; ENET_CMD <= 0; ENET_RD_N <= 1; ENET_WR_N <= 1; ENET_CS_N <= 1; oDATA <= 0; oINT <= 0; end else begin oDATA <= ENET_DATA; oINT <= ENET_INT; TMP_DATA <= iDATA; ENET_CMD <= iCMD; ENET_CS_N <= iCS_N; ENET_RD_N <= iRD_N; ENET_WR_N <= iWR_N; end end always@(posedge iOSC_50) ENET_CLK <= ~ENET_CLK; assign ENET_RST_N = iRST_N; endmodule  

 

Here's the componet overview: 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=8694  

 

Timing was taken from old DM9000A class.ptf.  

Based on those settings I get in signal tap this results: 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=8695  

 

when executing this code on NIOS: 

 

# define IO_addr 0# define IO_data 1 iow(0x1E, 0x01); void iow(unsigned int reg, unsigned int data) { IOWR(DM9000A_BASE,IO_addr,reg); usleep(STD_DELAY); IOWR(DM9000A_BASE,IO_data,data); }  

 

Value of reg 0x1E goes to the bus. 

Also CMD going up was rather strange. So in the second try I have changed address units WORD to SYMBOLS in my component. And here's the result: 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=8696  

 

Now I can even write the whole 16 bits at once, and CMD is gone. I suppose that it's not good that I get two 16 bit writes to the DM9000a. Perhaps it's related to the 32 bits that gets written by NIOS so it gives two clock cycles. I have provided only 16 bits, rest all zero. So my questions are: 

1) How to make only one 16 bit write ? 

 

2) The second IOWR(DM9000A_BASE,IO_data,data) - so writing the data (CMD should be high) never goes to the bus, CMD is always low. Any ideas why ? 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=8697  

 

I add DM9000A_hw.tcl packed in zip, so you can easily open it in QSYS and see my component. Also I have uploaded the whole project to Dropbox: 

 

https://www.dropbox.com/s/6ru77wyptaxcfdc/fpga_imgproc.rar 

 

Thanks in advance, 

Best regards, 

madness
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3 Replies
Altera_Forum
Honored Contributor I
43 Views

Hi, 

 

I was able to make it running.  

I have made no changes to NIOS code except changing this define: 

#define IO_data 4 

 

Also in the code the DM9000A.C file was included, which is rather bad so I only included .h file  

and had to move ether_addr table to .C file from .h. 

 

In my DM9000A component i have changed iDATA and oDATA to 32 bit and simply assigned  

lower 16 bits to ENET_DATA.  

I also resized iCMD to 8 bits and found out that bit 4 goes up when I write.  

So i simply assigned this bit to ENET_CMD. 

 

Also I changed read wait and write wait to 3 clock cycles in my DM9000A component (it's related to 100MHz clock for NIOS). 

 

Best, 

madness
Altera_Forum
Honored Contributor I
43 Views

 

--- Quote Start ---  

Hi, 

 

I was able to make it running.  

I have made no changes to NIOS code except changing this define: 

#define IO_data 4 

 

Also in the code the DM9000A.C file was included, which is rather bad so I only included .h file  

and had to move ether_addr table to .C file from .h. 

 

In my DM9000A component i have changed iDATA and oDATA to 32 bit and simply assigned  

lower 16 bits to ENET_DATA.  

I also resized iCMD to 8 bits and found out that bit 4 goes up when I write.  

So i simply assigned this bit to ENET_CMD. 

 

Also I changed read wait and write wait to 3 clock cycles in my DM9000A component (it's related to 100MHz clock for NIOS). 

 

Best, 

madness 

--- Quote End ---  

 

 

Is it true that regardless of the actual PHY chip, the mdio interface is common, and the device specific initialization is done in software? 

 

If so, couldn't an existing built-in qsys component (ex. LAN91C111) be instantiated, but registers initialized for the DM9000A? 

 

EDIT: Since these chips have MACs built-in to them, why is another MAC (Altera's TSE) added into the system design... how does that even work?
Altera_Forum
Honored Contributor I
43 Views

 

--- Quote Start ---  

Is it true that regardless of the actual PHY chip, the mdio interface is common, and the device specific initialization is done in software? 

 

If so, couldn't an existing built-in qsys component (ex. LAN91C111) be instantiated, but registers initialized for the DM9000A? 

 

EDIT: Since these chips have MACs built-in to them, why is another MAC (Altera's TSE) added into the system design... how does that even work? 

--- Quote End ---  

 

 

Hi happy, 

 

Where can I find LAN91C111 qsys component ? Is it ported to new quartus version ? 

 

Your statement about mdio does make sens. 

 

I don't see Altera TSE mac in the design that I posted. 

 

Best, 

madness
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