Hi,I try to setup DDR3 SDRAM from HPS on my Arrow SoCkit and then run bare metal application on it. I've installed HPS component in Qsys, set SDRAM controller parameters, make pins assignments with .tcl script generated. Quartus compiled the design and all DDR pins were routed. Then I generated spl preloader through bsp-editor and compiled it with Makefile. Bsp settings are gathered in attached file below. Then I load .sof file to the board and start to debug HPS through the DS-5 debugger. Preloader I've created doesn't work. Here is a script used to load & execute preloader on HPS:
stop wait 5s reset system wait 5s set semihosting enabled 0 loadfile "$sdir/u-boot-spl_my.axf" 0x0 set debug-from *$entrypoint start delete tbreak spl_boot_device cont wait 60sReset is all right. Loading log is:
Loaded section .text: S:0xFFFF0000 ~ S:0xFFFF690F (size 0x6910) Loaded section .rodata: S:0xFFFF6910 ~ S:0xFFFF84DE (size 0x1BCF) Loaded section .data: S:0xFFFF84E0 ~ S:0xFFFF93B3 (size 0xED4) Entry point S:0xFFFF0000 Target has been reset Execution stopped due to a breakpoint or watchpoint: S:0x00000000 S:0x00000000 LDR pc, ; = 0xA8We are in On-Chip RAM so it seems all rigth too. The next breakpoint is at 0xFFFF1310 (spl_boot_device) but it is unreachable:
ERROR(CMD360): # in C:\eclipse_work\Altera-SoCFPGA-HardwareLib-FPGA-CV-ARMCC\preloader.ds:46 while executing: wait 60s ! Wait for stopped timed out ERROR(CMD656): The script C:\eclipse_work\Altera-SoCFPGA-HardwareLib-FPGA-CV-ARMCC\preloader.ds failed to complete due to an error during execution of the script core 1 Current core is 1 (ID 1) interrupt Execution stopped at: S:0x00002FA4 S:0x00002FA4 LDR r1,It's jumped to 0x0000xxxx region (Boot ROM?), why? I try to debug it step by step with disassemble tool. Code from spl.c seems to start well, it enters to function spl_board_init() and then hangs in one of sys_mgr_frzctrl_freeze_req() functions (Freezing I/O banks section), but I'm not sure I'm right in this assumption. BOOTINFO reg = 0x000024A5 (BSEL = "SD/MMC", default board settings), INITSWSTATE reg = 0x00000100 (while valid value is 0x49535756 when preloader is loading to 0xffff0000 sector and it is valid -- is it important for this problem?) So how can I manage such a problem? Should I generate preloader with another settings or is it hardware problem? Any Ideas? Quartus II 14.1 and ARM DS-5 5.20.0 are in use. Thanks in advance.