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Altera_Forum
Honored Contributor I
1,253 Views

Problem in getting 1 usec Interval Timer to work using NiosII and QSYS

Hello everyone, 

Kindly guide me in resolving the following problem. I am unable to get the Interval timer to work for 1usec. It is working for 1msec. 

 

Case: I have a DE2115 kit. Using QSYS I have created a system that includes Nios II processor, few led outputs and 1 Interval timer.  

Interval timer setting: Timeout Period = 1 usec & Hardware options = Simple Periodic Interrupt, Counter Size = 32.  

Problem: 

In NiosII I have written a timer ISR that i assume should get invoked after every 1 usec, since the Timeout period is set to 1usec in QSYS. 

But i observed that the system behaves as if 1msec timeout period is set. in Interrupt I increment a variable and use this variable to toggle the LED on the board. I have used the LED on the board to observe the period. 

 

Are there any changes that i need to do in NiosII application if i select 1usec Timeout period 

 

thanks 

Jagdish
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10 Replies
Altera_Forum
Honored Contributor I
78 Views

I have not succeeded in working for 1 us with interrupt timer. The best I got is 15 us (without any other instructions) 

 

How do you set the period :  

by the Qsys component editor? 

maybe you have forgotten the "unit" ;-) 

 

Instead of using variable to undersample the inteerupt, you should just toggle the led, and put a scope on it. 

 

NB : you can use the full controlled interval timer, then you can change directly the period.
Altera_Forum
Honored Contributor I
78 Views

You aren't going to get a 1us timer interrupt working. 

At 100Mhz you only have 100 instruction clock cycles - you won't get into and out of the generic ISR code that fast.
Altera_Forum
Honored Contributor I
78 Views

I agree with mmTsuchi 

It's impossible to use 1us periodic interrupt on Nios. 

You must go at least to the 50-100us range, just to add a few instructions in isr and spare some headroom for non-irq code execution.
Altera_Forum
Honored Contributor I
78 Views

Thanks for the inputs. 

You'll have mentioned that 1usec is not possible.  

so just 1 question, Do we have any other alternative by which we can get 1 usec periodic interrupt. I am asking this because i foresee a need of time period less than 20 usecs.
Altera_Forum
Honored Contributor I
78 Views

Do you really need an interrupt? Why? 

Such fast work is usually implemented in hardware.  

It's should be an easy task here, since you are working with a fpga and you can overcome the harnesses of a common microprocessor.
Altera_Forum
Honored Contributor I
78 Views

You can get a more accurate timestamp by getting the hardware to count the ticks for you. 

You could also use a tickless timer scheme to get more accurate long intervals - but they'll still be subject to interrupt latency variations and the cost of the ISR dispatch. 

I'd guess that interrupt entry and exit both require a full flush of the instruction pipeline - probably 5 clocks each. You need to save and restore any registers, the register bank switching is probably also a pipelline flush. 

That is 20% of the cpu time (at 100MHz) before you do anything else. 

 

You aren't going to do anything withthat interrupt.
Altera_Forum
Honored Contributor I
78 Views

I got your points. basically I am a firmware guy and hence have a practice to use timer in the firmware to generate delays in firmware application. I am using FPGA for the first time and thought of using timer in the manner similar to the ones i used in microcontrollers. But now i shall work upon as suggested and try to fit in my requirements in hardware itself.  

thanks a lot.
Altera_Forum
Honored Contributor I
78 Views

If you want to delay for a few usec then loop reading a free running hardware counter until the value exceeds a calulated value (remember to use unsigned comparisons). 

I don't remember seeing an Altera supplied Avalon slave that is just a 32bit counter with a pre-divider, but they aren't that difficult to write.
Altera_Forum
Honored Contributor I
78 Views

There are a few possibilities[list][*]If you don't use a multitasking OS, a simple for loop that doesn't do anything can make a decent delay system. The Nios CPU doesn't have a lot of optimization bells and whistles, so this solution will be relatively stable. Just make a few runs with different values to calibrate your loop and find how many iterations per us you have. As long as you don't change the CPU clock frequency and have instruction cache, you'll always get the same delay. 

[*]add a second timer component in your SOPC/QSYS system, defined as "full featured". This timer can be started and stopped, you can define its period, and you can read its counter value. The timer will most of the time be stopped, and when you need to wait for a certain amount of time, set the timer period to the correct number of clock cycles and start it, in the "count down once" mode. Then if the delay is short, just poll the counter value and return when you reached 0. If it is longer then you can ask the timer to throw an interrupt when the value is reached. You need to be careful when using a multitasking OS, as this solution can only be used by one task at a time.[/list] 

You can find documentation about the interval timer here (http://www.altera.com/literature/ug/ug_embedded_ip.pdf) in chapter 28
Altera_Forum
Honored Contributor I
78 Views

Except that the 'timer component' is a 16bit slave (presumably it dates from the old 16bit nios) and it horribly expensive to access. 

For polled interval timers you only need a single counter that is always running (without a zero function), the software just needs to read the 'start time' when it starts a timer. 

For some uses you want to count clocks, for others divided down to usec, msec and seconds to avoid wrap issues for longer intervals.
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