10-25-2012 06:44 AM
I wrote a simple logic for cyclone-iii starter kit.I created the NIOS system with on chip RAM and few I/Os. (Here I didn’t include the CFI Flash) SOF download through Quartus II Programmer worked. From NIOS IDE , I used the tab ‘RUN as NIOS II Hardware’ to execute a simple program. This was also working. Now I modified the SoPC for external flash. I configured reset vector at flash address 0x000, and exception address at on chip ram 0x0000. Then a new BSP project is created in NIOS with new SoPC. The code is compiled. I used the same tab ‘RUN as NIOS II Hardware’ to execute a same program. While Programming it is showing the error. Please see the attached image. If I am trying to load it in flash then also it is showing the error. Check with the other image attached. Please review the issue and let me know is anything is to be corrected in the process. If any sample program is available for this exercise, then please suggest. I want to put both sof code and c-code in the flash memory.
10-25-2012 10:48 AM
I didn't think the CFI flash was directly byte/word addressable - which means you can't directly execute code form it.Certainly the jtag debugger can't download code to it - it won't have the code for the special flash write/erase sequences. When you load code from flash the reset vector points to an internal memory block that contains instructions to copy your code+data from the flash into 'normal' memory, either internal or external DRAM.
10-29-2012 10:52 AM
Does it mean we cannot laod NIOS II program in non-volatile memory.CYIII starter board has only parallel flash memory. For sof file, we can create pof file and some method is there to program. is there any way to program elf file in non-volatile memory?
02-27-2013 09:03 AM
Hi,I'm trying something simpler but similar. Obviously I'm a beginner. I use the Cyclone III starter kit, which comes only with a parallel flash memory, no EPCS. The question is how to write onto the flash. I read which pin is connected to which pin of the FPGA. I read something about the PFL flash programmer that has to be written onto the FPGA in order to write the programme onto the flash. I used the Altera tutorial to create a PFL-megafunction. My question is now how does everything go together? The megafunction has variables, which names don't match up with the flash. Additionally I get some "altera_reserved_..." pins in the pin planner that I don't know where to connect to. The length of the variables in the megafunction seem to be wrong (22 address bits but the flash uses 24). I used the correct CFI 128 chip to create the function. Any suggestion in which direction to head would be greatly appreciated. Cheers, Ulle