Re: Problem when downloading zImage to DE2-115 (cont.)

Altera_Forum · ‎04-30-2013

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This is jpe1313,

What I was saying was that are any of your entries your generated *.dts file "unknown." Take a look. If they are "unknown" then it COULD be a problem. For my custom design my "timer" was undefined and I had to define it properly. As far as the SD card. To clarify, I am not using the SD card in my design. I have a daughter card that has a Compact Flash.

Let me know if you need more help - but check your DTS

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I am not able to post without administrator's approval. So i sent my message here. I maybe wrote 5-6 times both topics but it seems all admins are sleeping. Please email me (occelebi at gmail) Because i can not send any message more than 1

Anyway, i have no unknown parameters.

/*

* This devicetree is generated by sopc2dts on Fri Apr 19 16:30:38 EEST 2013

* Sopc2dts is written by Walter Goossens <waltergoossens@home.nl>

* in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw>

*/

/dts-v1/;

/ {

model = "ALTR,onur";

compatible = "ALTR,onur";

# address-cells = < 1 >;

# size-cells = < 1 >;

cpus {

# address-cells = < 1 >;

# size-cells = < 0 >;

cpu: cpu@0x0 {

device_type = "cpu";

compatible = "ALTR,nios2-12.1";

reg = < 0x00000000 >;

interrupt-controller;

# interrupt-cells = < 1 >;

clock-frequency = < 50000000 >; /* embeddedsw.CMacro.CPU_FREQ type NUMBER */

dcache-line-size = < 32 >; /* embeddedsw.CMacro.DCACHE_LINE_SIZE type NUMBER */

icache-line-size = < 32 >; /* embeddedsw.CMacro.ICACHE_LINE_SIZE type NUMBER */

dcache-size = < 2048 >; /* embeddedsw.CMacro.DCACHE_SIZE type NUMBER */

icache-size = < 4096 >; /* embeddedsw.CMacro.ICACHE_SIZE type NUMBER */

ALTR,implementation = "fast"; /* embeddedsw.CMacro.CPU_IMPLEMENTATION type STRING*/

ALTR,pid-num-bits = < 8 >; /* embeddedsw.CMacro.PROCESS_ID_NUM_BITS type NUMBER */

ALTR,tlb-num-ways = < 16 >; /* embeddedsw.CMacro.TLB_NUM_WAYS type NUMBER */

ALTR,tlb-num-entries = < 256 >; /* embeddedsw.CMacro.TLB_NUM_ENTRIES type NUMBER */

ALTR,tlb-ptr-sz = < 8 >; /* embeddedsw.CMacro.TLB_PTR_SZ type NUMBER */

ALTR,has-mul; /* embeddedsw.CMacro.HARDWARE_MULTIPLY_PRESENT type NUMBER*/

ALTR,reset-addr = < 0xc0000000 >; /* embeddedsw.CMacro.RESET_ADDR type NUMBER */

ALTR,fast-tlb-miss-addr = < 0xc8001000 >; /* embeddedsw.CMacro.FAST_TLB_MISS_EXCEPTION_ADDR type NUMBER */

ALTR,exception-addr = < 0xc0000020 >; /* embeddedsw.CMacro.EXCEPTION_ADDR type NUMBER */

}; //end cpu@0x0 (cpu)

}; //end cpus

memory@0 {

device_type = "memory";

reg = < 0x08001000 0x00000400

0x00000000 0x08000000 >;

}; //end memory@0

sopc@0 {

device_type = "soc";

ranges;

# address-cells = < 1 >;

# size-cells = < 1 >;

compatible = "ALTR,avalon", "simple-bus";

bus-frequency = < 50000000 >;

jtag: serial@0x8001440 {

compatible = "ALTR,juart-12.1", "ALTR,juart-1.0";

reg = < 0x08001440 0x00000008 >;

interrupt-parent = < &cpu >;

interrupts = < 1 >;

}; //end serial@0x8001440 (jtag)

timer: timer@0x8001420 {

compatible = "ALTR,timer-12.1", "ALTR,timer-1.0";

reg = < 0x08001420 0x00000020 >;

interrupt-parent = < &cpu >;

interrupts = < 0 >;

clock-frequency = < 50000000 >;

}; //end timer@0x8001420 (timer)

}; //end sopc@0

chosen {

bootargs = "debug console=ttyJ0,115200";

}; //end chosen

}; //end /

And i also made my friend compile my kernel and .sopc file and tried to new zImage but terminal gave me same output :/

root@F15:~# altera/12.1/nios2eds/bin/nios2-download -g /home/student/Downloads/zImage

Using cable "USB-Blaster [8-1]", device 1, instance 0x00

Pausing target processor: not responding.

Resetting and trying again: FAILED

Leaving target processor paused

I hope you can even help further.

Regards,

Cem

Altera_Forum · ‎04-30-2013

Hello,

Usually if your processor can't be even reset the problem is your processor is not running. It will happen if you have no clock. Also, check your compilation report for critical warnings. Unassigned pins may cause this problem too. Check for timing issues. If you have a processor with the jtag-debug enabled and the processor is running then the processor should be successfully reset through the jtag debug interface by the nios2-download command.

Altera_Forum · ‎05-01-2013

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Hello,

Usually if your processor can't be even reset the problem is your processor is not running. It will happen if you have no clock. Also, check your compilation report for critical warnings. Unassigned pins may cause this problem too. Check for timing issues. If you have a processor with the jtag-debug enabled and the processor is running then the processor should be successfully reset through the jtag debug interface by the nios2-download command.

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Thank you for your help. There are such a clock which i dont know where to assign them. So i paste here all critical errors.

Critical Warning (332012): Synopsys Design Constraints File file not found: 'onur.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.

Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.

Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)

Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)

Critical Warning (332169): From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)