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Altera_Forum
Honored Contributor I
766 Views

Problem with Pin out not corresponding to the settings in my design

I am usign Quartus II to program an FPGA Cyclone 3. I am including the Nios Processor in my design. 

 

I had it working initially satisfactorily. However, I made a few additions and modifications and for some reason the pins that I programmed as outputs are not responding. For example, I have an Avalon port on the nios called PING. This port is connected to an output ping. I have acecss to that pin in my hardware. When my software toggles the port, I cannot see the change in the pin. The port PING is not the only one that is not responding, there are two more, all of them are avalon PIO ports.  

 

As I said everything was working before. I do not know if I corrupted something in the settings or exceeded some design thresholds. 

 

I have checked and rechecked my sopc assignments. I have also regenerated the sopc, created new projects and BSPs to make sure all my system is upto date but I still have the problem. 

 

I am using Eclipse to develop and test my software. In the debuggin process I have even tried to control the ports that are not recsponding via me memory window. I can control the ones that are ok, but not the PING port and the others. 

 

At this time I am stripping down my design to a bare minimum to see if I can get to a point in which the remaining parts of the system behave properly. The problem is that each compilation takes 40 minutes... it is a pain. 

 

Any suggestions? 

 

Thanks
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2 Replies
Altera_Forum
Honored Contributor I
23 Views

Did you check fpga pin assignments? 

You can also try Signaltapping the pio output or loopback it to a pio input.
Altera_Forum
Honored Contributor I
23 Views

 

--- Quote Start ---  

Did you check fpga pin assignments? 

You can also try Signaltapping the pio output or loopback it to a pio input. 

--- Quote End ---  

 

 

 

Cris72, 

 

Thanks for the advice. I did signal tapping (looping the output to an input) and things were fine. However, after a careful checking of the FPGA pin assignments I noticed I had assigned one pin wrongly. I fixed it and my problem is solved now.