Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Valued Contributor III
716 Views

Problem with SDRAM on DE2 board

I am using the Altera DE2 board (Cyclone II FPGA), Quartus 8.0 and Nios II IDE 8.0. I am having trouble using SDRAM in my design. Following are the details: 

 

1. I have included a PLL component in my design. Phase shift is -54 deg (-3 ns) and the output of the PLL is connected to the SDRAM clk. 

 

2. I have set the reset vector and exception vector of my Nios II processor to be in the SDRAM (within the SOPC builder). 

 

3. While building the system library for my application (inside the Nios II IDE) I specify the heap, stack, text memory to be SDRAM.  

 

There is no compilation error within Quartus II or build error inside Nios II IDE. compilation and build are successful. But when I try to run the application, there is no output. The Nios II output terminal opens, and the console remains blank. When I change the settings mentioned in points 2 and 3 above to 'SRAM' the application works perfectly and prints the output to the console. 

 

I kept the above settings as 'SRAM' and tried to "test" the SDRAM by reading to and writing from it (Reference: 'Rapid Prototyping of Digital Systems' by Hamblen). The "test" was positive. Returned no errors.  

 

Is there any other setting for the SDRAM that I am missing? 

 

I would appreciate any help/insights. 

 

Thanks!
0 Kudos
6 Replies
Highlighted
Valued Contributor III

Re: Problem with SDRAM on DE2 board

I found a description and solution to this problem in this document from Altera: 

http://www.altera.com/literature/hb/nios2/n2cpu_nii51005.pdf 

 

The problem, apparently is related to the tuning of the PLL phase shift. The document describes how to adjust the phase shift. Mine worked for a phase shift of -45 deg (-2.5 ns).
0 Kudos
Highlighted
Valued Contributor III

Re: Problem with SDRAM on DE2 board

I am using the same configuration (DE2 Cyclone 2) and I have the same problem with the SDRAM.  

(the program does'nt launch after downloading: Starting processor at address ... then NIOS console remains blank ) 

I'm just trying to run an helloworld exampe program from SDRAM. 

Reset vector and exception vector of nios are in SDRAM. 

Linker setting: .bss .heap .rodata .rwdata .stack .txt => SDRAM 

i tried different tuning of the pll but it does'nt change anything. 

If someone have any ideas, I would be happy to try !
0 Kudos
Highlighted
Valued Contributor III

Re: Problem with SDRAM on DE2 board

Ok I get it. I found my mistake myself. I just don't used the good tunning of the PLL.

0 Kudos
Highlighted
Valued Contributor III

Re: Problem with SDRAM on DE2 board

What is the good timing for DE2 board? Because I set a lot of values and still I've got error with verifing data from sdram when I program NIOS.

0 Kudos
Highlighted
Valued Contributor III

Re: Problem with SDRAM on DE2 board

0 Kudos
Highlighted
Valued Contributor III

Re: Problem with SDRAM on DE2 board

0 Kudos