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Altera_Forum
Honored Contributor I
840 Views

Problem with UART receive

Hi, 

I have designed a board with Cyclone-IV E FPGA with UART interface (just Rx and Tx) and some other connections. I built a Qsys system with NiosII/e processor, UART and some other peripherals. I have not connected the UART core to IRQ. In the SDK environment, I built the BSP with reduced device drivers and small C library.  

 

I opened a hypterminal and connected the cable between my board and the PC. I can see that writing a character to the txdata register gets reflected in the hyperterminal window: 

IOWR(UART1_BASE, 1, 'X'); 

 

I can also see that if I loop back the Tx pin to the Rx pin at the NiosII system boundary, and write a character to the txdata register, it immediately gets reflected in the rxdata register (I am seeing the Memory map view in the Debug perspective).  

 

Now when I send a character from the hyperterminal, I don't see it getting updated in rxdata register. I tried reading the rxdata register and writing it to the txdata register. The displayed character in the hyperterminal is not the same as was sent.  

 

I am also seeing that the status register is always 0x60. The byte following it always 0x00. It is a great wonder. The status register is supposed to be 12 bit wide according to the datasheet. How am I supposed to interpret the value stored there.  

 

I had seen an example application (AN459). It is about UART bit-bang. In that, they check for the TRDY bit and then send the next character. They use: 

while (!(uart_status = IORD(UART1_BASE, 2) & 0x40)); 

 

In my case this returns true and the loop exits. That means the upper 4 bits (EOP, CTS, DCTS, E) are totally dis-regarded! (0x60 & 0x40) returns true. That means the first byte stands for (RRDY, TRDY, TMT, TOE, ROE, BRK, FE, PE). Where is the storage for the upper four bits?  

 

The RRDY is never going high. Even in the case of Tx and Rx pins being shorted at the FPGA boundary.  

 

Can someone please help me with this. 

 

regards, 

rajesh
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3 Replies
Altera_Forum
Honored Contributor I
103 Views

I figured that the upper four bits of the status register are in the byte following the lower byte in the memory map. The bytes must be stored in little-endian format, though no user guide mentions this.  

 

Going by some threads, I figured that the IRRDY interrupt must be disabled. It worked for some guys. But unfortunately for me, even this is not working. RRDY simply refuses to go high.  

 

I checked the waveforms being transmitted from the PC. They look perfect.  

 

The biggest wonder is that even a simple loopback between Tx and Rx refuses to set the RRDY bit, even though I can see in the memory map that the byte written into the txdata register has got reflected in the rxdata register. This is in spite of the IRRDY interrupt being disabled.  

 

I have tried this in Quartus 11.1 and 13.1 with same effect.  

 

Any help will be greatly appreciated. 

 

regards, 

rajesh
Altera_Forum
Honored Contributor I
103 Views

I finally fixed the bug. The problem was in the PCB. The connection to the DB-9 connector was wrong. Pins 2 & 4 were interchanged. The pins were arranged in reflected order. So Rx was not getting the signal. Now it is working great!

Altera_Forum
Honored Contributor I
103 Views

Hi atrajesh, 

 

I have met the same problem. When the PC sent a char to FPGA, I can get the right char though Rxdata register. But the RRDY bit never changed. Did you get the right RRDY bit after your PCB modification?
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