Re: Problem with burstcount > 2 for Avalon MM Master to SDRAM

Altera_Forum · ‎03-11-2013

Hello,

I am trying to implement a burst transcation with SDRAM using Avalon MM Interface.

The following Verilog code works fine for burstcount = 2:

module hw_det_3by3(
    clk, 
    reset,
    avs_csr_addr,
    avs_csr_write,
    avs_csr_writedata,
    avs_csr_read,
    avs_csr_readdata,
    avm_sdram_addr,
    avm_sdram_burstcount,
    avm_sdram_read, 
    avm_sdram_waitrequest,
    avm_sdram_readdatavalid,
    avm_sdram_readdata
    
);
input wire clk;
input wire reset;
input wire  avs_csr_addr;
input wire avs_csr_write;
input wire  avs_csr_writedata;
input wire avs_csr_read;
output wire  avs_csr_readdata;
output wire  avm_sdram_addr; 
output wire  avm_sdram_burstcount;
output wire avm_sdram_read;
input wire avm_sdram_waitrequest;
input wire avm_sdram_readdatavalid;
input wire  avm_sdram_readdata;
reg  read_addr;
reg load_minors = 0;
reg count = 0;
reg status = 0;
reg  minor10;
reg  minor11;
reg  minor12;
reg  minor20;
reg  minor21;
reg  minor22;
reg sdram_read;
reg  csr_readdata;
assign avm_sdram_addr = read_addr;
assign avm_sdram_burstcount = 2;
assign avm_sdram_read = sdram_read;
assign avs_csr_readdata = csr_readdata;
always @ (posedge clk)
begin 
    if (avs_csr_write == 1)
    begin 
        if (avs_csr_addr == 1)
        begin
            load_minors <= 1;
            read_addr <= avs_csr_writedata;
        end
    end
    if (load_minors == 1)
    begin
        load_minors <= 0;
    end
end
always @ (posedge clk)
begin
    if (load_minors == 1)
    begin
        sdram_read <= 1;
    end
    else
    begin
        if (avm_sdram_waitrequest == 0)
        begin
            sdram_read <= 0;
        end
    end
end
always @ (posedge clk or posedge reset)
begin
    if (reset == 1)
    begin
        count <= 0;
        status <= 0;
    end
    else if(avm_sdram_readdatavalid)
    begin
        case (count)
        0: begin
                minor10 <= avm_sdram_readdata;
            end
        1: begin 
                minor11 <= avm_sdram_readdata;
                status <= 1;
            end
        endcase
        count <= count + 1;
    end
end
always @ (posedge clk)
begin
    if(avs_csr_read == 1)
    begin
        case (avs_csr_addr)
        0: csr_readdata <= status;
        1: csr_readdata <= read_addr;
        2: csr_readdata <= minor10;
        3: csr_readdata <= minor11;
        endcase
    end
end
    
endmodule

Software Interface in NIOS:

#include <stdio.h># include "system.h"# include <io.h># include <stdlib.h> /* rand(), RAND_MAX */
int main()
{
    float n = 1.25;
    float m = 2.5;
    printf("%x, %x\n", &n, &m);
    IOWR(HW_DET_3BY3_0_BASE, 1, &n);
    while (IORD(HW_DET_3BY3_0_BASE, 0) == 0){
        printf("%x\n", IORD(HW_DET_3BY3_0_BASE, 0));
    }
    printf("%x\n", IORD(HW_DET_3BY3_0_BASE, 1));
    printf("%x\n", IORD(HW_DET_3BY3_0_BASE, 2));
    printf("%x\n", IORD(HW_DET_3BY3_0_BASE, 3));
  return 0;
}

However, when I make slight variations to implement the same functionality for a burst of 3 words, then I get problems - 'status' never changes to 1.

Does anyone have an idea why that is? I have been trying to solve this for the past few hours now...

Also, is there are a possibility I can monitor my signals (avm_sdram_writerequest, avm_sdram_readdatavalid etc.) during runtime?

Many thanks in advance.

Jimmy

Altera_Forum · ‎03-12-2013

> Also, is there are a possibility I can monitor my signals (avm_sdram_writerequest, avm_sdram_readdatavalid etc.) during runtime?

Hi,

Have a look at the signal tap logic analyzer included in Quartus. Very useful for tracking down this kind of thing and it will allow you to see the signals in action and trigger on their state.

Mark.

Altera_Forum · ‎03-12-2013

Many thanks for the tip, this already helped me to identify several mistakes.

Is there also a tool to monitor SDRAM content at runtime?

Had a look at In-System Memory Content Editor, but seems like it only supports on-chip memory... (I am using the SDRAM Controller Component in Quartus).

Altera_Forum · ‎03-13-2013

> Is there also a tool to monitor SDRAM content at runtime?

You could make an Avalon master that reads an address. Connect both that and your other stuff to the memory - Qsys will take care of adding arbitration. Or get your "test" master to read through a range of address and monitor the results with SignalTap.

Mark.

Altera_Forum · ‎03-20-2013

I would just simulate your design so that you can view everything to perform proper debug.

Although I'm not sure why the status bit does not assert, I think you want your count register to be two bits wide otherwise you will end up overriding the value in minor10 due to count register rolling over.