Hello,I am having a really weird problem. I have a design in the form of an .sof and .sopc file and some code which I have written to run on top of this. I am using the DE1-SoC board. This setup works perfectly fine for 3 boards that I have. Today I got a new board - exactly the same revision and family, and the code is just not loading on the FPGA. I get the following error Expected system ID base address: <base addr> Expected system ID: <system id> Connected system ID: Not Found Expected system timestamp: <timestamp> Connected system timestamp: Not Found I know that this is not a design issue because I can still use the same sof on all the other boards and the same elf file loads fine. I have no idea what is wrong with this new board. I've even tried this on multiple computers. For some reason, on one of the laptops, the new board worked ONCE - and thats it. Same problem after that. I can't even replicate that ONCE event anymore. I am using v16.00 of the lite tools from the Altera website. Any idea about what can be wrong? or what I can try. Is there a way to validate the health of the board? Its a new board, but maybe that's worth a shot. Thank you
Hi,Could you give a quick try by creating a simple hardware maybe some blinking LEDs to ensure the SOF file can be programmed into the device? Just ignore the software part for this experiment as if you have programmed the SOF successfully usually you will be able to see the system ID and timestamp.