Hi to everyone! We need to flash Fpga configuration + NiosII software (to boot application "on place"). This method runs with older versions. Attempting to write SOF + ELF on flash (with common USB Blaster) we have always, after two good answers during process, an error 8 , reported on attached file. This stop all our attempts to boot an embedded sw application for Nios on our HW... do you meet similar issues recently? Thanks on advance for any idea or support!
Looks like the USB blaster or download cable wasn't able to detect the FPGA and devices correctly. The error problem with JTAG chain suggests that the programmer could not verify the devices in the setup via the JTAG port. Are you using the correct port for JTAG configuration and is the MSEL settings set appropriately.
Thanks, Abr! Connection should be ok, as per device ack... I can work every time with NiosII Jtag from Eclipse for long debug sessions of developing software. The problem occours when I attempt to program Flash using Sof+Elf. First 2 steps runs fine (see "buono" on report window attached..).. sfter first 2 steps programmer fails with "8" code error... but connection seems valid. Msel could involves only Fpga boot mode... not during programming....
Hmm, since you say its working with the NIOS2, I assume you are using the JTAG UART port. This port is different from the JTAG programming port. I suggest you look at the board for another JTAG port that is connected to the FPGA. This JTAG port may be the one for programming the FPGA.
Are you using an Intel FPGA Kit or is it a custom board? Can you share the FPGA schematics if possible so that I can check the connection of the JTAG ports?
Hi abrham if you read ug_nios2_flash_programmer guide on pag 6 , you can see capabilty to program FLASH via Jtag (Passing on FPGA), this is made from SBT ECLIPSE Flash programmer.
You must load Hardware (SOF FILE), then add Nios SW (ELF FILE)
FInally, start programming flash. After first 2 succesfully steps. we have Error 8 attached messge..
We already used this feature many times on other hardware. Now with Quartus 18 probably we meet this issue.... if anyone know the question.....
Have you recompiled your design after upgrading to v18 of quartus? I'd suggest you recompile both the HW as well as the SW design and then try programming it. You can also try re-intstalling the Quartus Programmer tools and then try.
After Intel traslation from Altera, we found serios degradation of documentation and support. Many links to help files are lost on Quartus. I found problems running modelsim, and I must solve them manually, by TCL modifications. I hope that INTEL will give a professional effort to FPGA questions, or we may think to different brands to plan realiable projects!