I have a dev kit DE5-NET (from terasic) with Arria 10 (10AX115). In my project I use PCIe hard IP. After I was download a firmware into CFI flash memory I power on a PC with FPGA board. In my PC instantiated Intel Xeon CPU (I dont know which model). And after power on OS (Linux) doesn see a FPGA device on a PCIe bus. In signal tap I see that doesnt up links (ltssmstate switch between 0 and 1 values). After reboot without disable power nothing changes. But when I download a SOF firmware after reboot I see a PCIe device.
And also into another PC load from CFI flash work correctly (I was test it with Intel i7 CPU and windows).
Help me please. Why PCIe controller cant a configure? I use PCIe GEN1 4 lines. I was try use SW reset together with HW reset.
I setup MSEL for parallel programming (as described in a user guide) I download a firmware into a flash memory with special design, it was presented by terasic. My firmware downloaded is correct (i can run a signaltap that included in a design). The same board with the same firmware load correctly with i7 processor and windows OS.
Now I can run a firmware after reset: I power up a PC, after it run I doesn see a PCIe device and after reset without power down PCIe links correctly setup. For this I change settings in PCIe controller "Endpoint L0 and L1 acceptable latency on a no limit.
It looks like your Linux setup is not able to detect the FPGA during the initial power up boot is because the FPGA is not able to meet the PCIe wake up time. I would recommend you to use CvP in order to meet the PCIe wake up time