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Programming EPCS via NiosII IDE

Altera_Forum
Honored Contributor II
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I have a custom NiosII Cyclone board with both a JTAG header and an EPCS header (active serial). I have been using the Quartus programmer utility to update my single EPCS device with the project .pof file, and using the Eclipse flash programmer utility to update my single flash device whenever the SW changes. After reading the flash programmer doc, it sounds like I might be able to program both devices thru the JTAG header, but so far no luck. The flash programs fine, but I get a "no rule to make NII.sof". NII is the name of the target CPU, but there is no NII.sof anywhere.  

 

I have selected "Write NiosII FPGA config (.sof)" option in the flash programmer dialog, but I notice that the "to device and offset" pulldown contains the same invalid NII.sof filename, which looks like it came from the flash programmer project. Confusing, since the flash programmer sof was already successfully loaded to burn flash. How can I change this dialog to point to my real application sof file? 

 

When I create the flash programmer project, do I need to specifically add an EPCS device interface? 

 

The flash document also talks about a few other configurations: 

A) Burning both the SW(srec/flash) and HW (pof/sof) into an EPCS device. This only seems useful for small SW images.  

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/cool.gif Burning both to a flash device. This does not make a lot of sense for my HW. It sounds like you would still need a hard processor or EPCS device anyway, so what&#39;s the point?
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Altera_Forum
Honored Contributor II
103 Views

Has anyone successfully programmed an epcs active serial device using the flash programmer utility in Eclipse? 

 

I have tried a few things, but have not gotten any further. The flash does program, but then I get the error "no rule to make EPCSimage", where EPCSimage is the hw image name for my asmi module (as defined in the flash programmer project). 

 

My application sof & pof are already made, so what further steps are needed? 

 

Do I need to manually edit the makefile to add a rule for making this hw image? If so, what should the rule do?  

 

thanks
Altera_Forum
Honored Contributor II
103 Views

Hello tns1, 

 

We have had the same configuration problem. We have serveral boards with both JTAG header and EPCS header. One for debug and one for EPCS programming. I we could just use one header this would be much easier. 

 

The way to program he EPCS through the JTAG header, we used the Quartus 4.1 programmer. 

In Quartus under File there is a menu option Convert Programming files. Open this menu item en then select for JTAG Indirect configuration file. 

Then select your EPCS device and add your .sof file and press OK. 

 

Then use the Quartus programmer to open your *.jic file. The programmer now recognises your cyclone device and EPCS device. 

It loads a special memory image for the cyclone device to programm your EPCS device. This is all done through the JTAG header. 

 

Good Luck
Altera_Forum
Honored Contributor II
103 Views

Andre, 

Thanks. I tried it and it and it seems to work.  

One problem is after I programmed the device thru the Jtag, I tried to verify the image using the EPCS (active serial) header as a check.  

The verify failed. Should the images produced be identical, or are there some formatting differences? 

 

Although this a definite improvement over the two-header programming method, it does still require two different files. If both the EPCS device and the system flash could be programmed with the Flash Programmer Utility in Eclipse, that would be easier still.  

There is a NIOS document "EPCS device controller core", which says that the older ASMI module which I included in creating a Flash Programmer Project, should be replaced with the EPCS controller module. I am hoping this is the answer. So far the fitter complains about allocating space in the EPCS device, so I must have something set wrong.  

 

I&#39;ll post if I get it to work. 

 

Thanks again.
Altera_Forum
Honored Contributor II
103 Views

Finally I able to program both my onboard flash memory and the serial flash (EPCS) all from the flash programmer utility using only the Jtag header in one step. This is method seems preferable when you have to do in-the-field upgrades that may include both HW & SW. 

 

The steps are these: 

1) Modify or create a new flash programmer project. Make sure to use the --epcs flag in mk_target. Delete the default ASMI module and add an EPCS controller module. I had to do this in two steps (delete asmi, regenerate, add epcs, regenerate) because of SOPC errors. My flash programmer project would not compile until I reduced the payload buffer component from 2K to 1K.  

 

2) Open your application in SOPC and select your newly created flash programmer as the target (thanks Nate). Regenerate and compile. 

 

3) Open Eclipse and create a new SW &#39;hello world&#39; project & build all. Open the flash utility. Create a new flash configuration with a unique name. Browse to your application. Check the box &#39;Write NiosII FPGA config&#39;. The path should point to your main application sof. If it doesn&#39;t see step 4. 

 

The utility will 1st program the flash memory, then convert the sof config file to an rbf and then program the epcs device.  

 

4) If you have any problems like you can&#39;t get the flash utility to talk to the board, or you see incorrect files being invoked in the programmer, shut everything down and re-open the files. Go back to step 1 and double-check your settings, re-generate, re-compile where possible.
Altera_Forum
Honored Contributor II
103 Views

Your steps look just right to me. Except you shouldn&#39;t have to replace the ASMI controller with the newer EPCS controller.  

 

It is true that we generally recommend the EPCS controller over the ASMI component. However the flash programmer design contains an ASMI for a reason. The main difference between the two components is that the EPCS controller contains a bit of on-chip memory that allows you to boot a NiosII from the EPCS device (you can&#39;t boot from an ASMI). Since the flash programmer design boots from on-chip rom, not the EPCS, there is really no need for the EPCS controller over the ASMI. The reason the ASMI controller was chosen for the flash programmer design is that it does not consume the memory resources the EPCS controller does, allowing the flash programmer design to fit in the smallest Cyclone device, a 1C3. This is why your controller swap is likely the reason you needed to reduce the size of your payload buffer memory.  

 

I suspect your list of steps would also work without replacing the ASMI with an EPCS Controller.
Altera_Forum
Honored Contributor II
103 Views

It seems I spoke too soon in claiming victory. I had two HW images defined in the flash programmer project, a &#39;sw_app&#39; image for the SW stored in parallel flash(seems unnecessary), and a &#39;hw_app&#39; image for the serial epcs. When I tested with the flash utility, I did not notice that it was the &#39;sw_app&#39; image that was specified in the pulldown dialog. It appears that it first programmed the parallel flash with the sw application flash.flash file, and then wrote over this with the hw application sof converted to a rbf.  

 

When I go back and select &#39;hw_app&#39; in the flash utility, I get the same old "make: No rule to make hw_app" I was getting before. Is the makefile generator supposed to add this rule automatically, and if not, how do I do it?  

 

Nate, on your advice I have gone back and restored the ASMI module and removed the redundant sw_app image, but I get no further. 

 

BTW, whenever I modify the flash programmer project (such as renaming my hw image or base address), I need to re-generate and recompile it and the application project and the sw project twice before the changes I made propagate thru to the flash utility dialogs.
Altera_Forum
Honored Contributor II
103 Views

tns1, 

 

Don&#39;t give up! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif  

 

This feature is one of the biggest draws for us to NiosII/Eclipse. If it can work, I hope you figure it out soon. Better yet, I hope this critical feature is made an order of magnitude simpler. 

 

I still don&#39;t quite understand the need for so much setup. It&#39;s not like the EPCS has variable pin-outs. 

Probably missing something here, but couldn&#39;t interface simply allow us to select the .SOF, .srec, and an address for the bootloader to use? 

 

Since the bootloader is no longer needed once booted, it could reside almost anywhere. Or a simple to use alternative would be a Bootloader IP in SOPC that you add to your design and set your reset vector to. It&#39;s my understanding that the bootloader code only requres a single M4k block. 

 

Ken
Altera_Forum
Honored Contributor II
103 Views

In the past, I have used the Jtag indirect (jic) file to program the fpga configuration device on my boards. I have used the Quartus programmer utility launched from either Quartus or the NiosII IDE. For some reason the same jic files I used just the other day won&#39;t download now. I get a "serial flash loader IP not loaded on device 1". The hw is fully functional and the jtag port is working fine. What step am I missing here?

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