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Altera_Forum
Honored Contributor I
675 Views

Programming second CPU

Hello 

 

I'm using a Cyclone III starter board and trying to build a system with 2 cpu's but can't get them to work together. 

 

I've got both in one SOPC system. 

CPU1 has a reset vector of ext_flash 0x0 and exception vector onchip_ram 0x20 

 

CPU2 has a reset vector of ext_flash 0x800000 and exception vector onchip_ram2 0x20 

 

I generate the SOPC system and build it in Quartus and then do the convert progamming file etc bit to create the .pof and write it to the board. 

 

Then in NIOS II eds I've got three projects (one for each CPU and a BSP). I build them and then use the flash programmer to write the two elf's to the flash. I've set the flash offset in the programmer to 0x800000. When it intially writes to the flash everything works fine (both CPUs are running) but when I cycle the power on the board only one of the CPUs starts.  

 

Where am I going wrong?
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5 Replies
Altera_Forum
Honored Contributor I
39 Views

Did you only program the flash at 0x800000? I could see that being the problem since only CPU2 could boot properly in that case. CPU1 is expecting it's software to be located at 0x0 so you would have to flash program that location as well. 

 

Also you mentioned you are using the same BSP for both applications. Since you are trying to boot two processors I recommend giving each one it's own BSP (each processor has their own view of the system so using using the same BSP will cause all kinds of problems).
Altera_Forum
Honored Contributor I
39 Views

Sorry, that part of my message wasn't very clear. I'm using the NIOS II Flash Programmer and pointing it to my sopcinfo file. I then add the two .elf files - leaving cpu1 with <no offset> and setting the offset for cpu2 at 0x800000. It programs ok and both CPUs start but when I cycle the power to the board only one of them starts up again.

Altera_Forum
Honored Contributor I
39 Views

I've used 2 cpus, but I exposed the soft reset lines and only released the cpus once all the code was in place (loaded by an external Avalon master). 

If the two cpus share any resources (or communicate through shared memory) you might want to get one of them to load all the code then release the second from reset. 

 

You could possibly run code on the cpu that works to find out whether the other cpu has performed any of its reset code.
Altera_Forum
Honored Contributor I
39 Views

I bet BadOmen has it right with the single BSP causing problems. I don't think it would work without changing the linker script address ranges in the BSP for each processor.

Altera_Forum
Honored Contributor I
39 Views

Thanks for your help everyone. I'm going to have another go at this today. I've actually managed to get it to work with a Cyclone II Starter Board. I did use two bsp's and programmed the flash twice rather than trying to write them at the same time. This worked.

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