Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12436 Discussions

Purchase of New Intel FPGA Development Board

TechDeveloper
Novice
878 Views

Dear Sir:

 

     I am an FPGA programmer (Xilinx programmer) and I would like to sample the Intel/Altera development IDE.   

     I am interested in purchasing a development board.     However, I would like to know what I will receive for my purchase.    

     For example, what are the limits of the free software Quartus Prime Lite Software?   

For example:   

I was considering purchasing the  Intel® Cyclone® 10 LP FPGA Evaluation Kit

Cyclone 10 LP Evaluation Kit (intel.com)

 

However, I read this:

"...Intel MAX 10 FPGA, pre-programmed System Manager ASSP functions (Not programmable by the user)"

Can anyone tell me what "...(Not programmable by the user)" means in terms of software development limits?

Also,  

When I looked at the software examples I noticed that they make reference to Quartus Prime Standard, not "Quartus Prime Lite".  I have linked the webpage.

Design Store for Intel® FPGAs

Will these design examples work using Quartus Prime Lite?

 

Last question:

 

I am interested in downloading and using the soft processor Nios II, can I download this soft processor onto this development board and will the Nios II flash programmer work on this board and be able to program an external flash IC that I have interfaced to an external port (assume that the external flash IC is "supported" brand by Intel/Altera)?

 

Note:  If you don't understand my question, Xilinx offers a soft processor (IP processor that is created by code - not a hardened processor that is composed of semiconductor material),  that the developer can download onto their development board.     I am assuming that the Nios processor is downloadable into the FPGA.

 

Thank you for your consideration.

 

0 Kudos
1 Solution
James_B
New Contributor II
833 Views

Thanks for the Kudos. I do understand . . . I have had the same issues.

From a high level / top level viewpoint, you will be able to update the RELEASE version of the download if need. 

 

Overall here are the details:  

Basically, there is no First Stage Boot Loader with Nios (compared to something like Zynq 7000 series for example.) The Cyclone 10 LP does not have an ARM A53 or A9 in it . . . so you will have to use Nios and Nios can boot directly from internal memory if the program fits within your internal RAM. For most Nios programs, say 64K to 128Kbytes of memory is sufficient ... and the Cyclone 10 LP should have enough internal RAM (and I believe it also has HyperRam attached to it that you can access) that you should be okay. 

Basically, you can program the flash memory through the USB blaster, and when the FPGA boots the Nios program will be in the flash. You just have to convert the ELF file in Eclipse using mem_init_generate for make targets in Eclipse to convert the ELF to hex, and then attach the hex to your Quartus project and compile ... and the Nios instructions will be in the external flash memory. So in summary: 

1. Develop your C in Eclipse, JTAG downloading your design and testing 

2. When finished, convert ELF to hex with mem_init_generate in Eclipse

3. Attach hex to Quartus project

4. Compile Quartus project

5. Program flash memory with Quartus programmer

When you power cycle, you should see your Nios software executing (such as through Uart, led, etc.)

Regards, James

View solution in original post

9 Replies
James_B
New Contributor II
854 Views

TechDeveloper - Basically, the Nios II processor comes into two primary versions, II/e and II/f. (There is also a middle version, II/s) In short, when you setup Nios II in your design, the II/e version will be "free" and you won't have any issues using it in a design in terms of using Quartus Lite and the II/e. However, if you want the single cycle multiplier and memory management (MMU) options for the processor (among other things) you will need to get a Nios embedded license, which is about $500 I believe at the time of this writing. You can get these licenses from Mouser, Digikey, etc. I have done many Microblaze designs, as well as Nios, and the main difference is that Microblaze doesn't have a tiered systems for $ per features. In short, the Nios II/f is an IP that has to be purchased : 

1. Nios II/e - free

2. Nios II/f - not free 

 

Now onto your second question - the Max10 System Manager contains code for the USB blaster JTAG programmer and that is not free either, that is why it is programmed into the chip but the source code is not available. 

Regards, James

 

TechDeveloper
Novice
848 Views

Hi, James!

 

      Thank  you for your informative reply.   

 

       Since I am primarily a Xilinx programmer and Xilinx gives away its IDE free of charge (Vivado + Vitis) when you wrote:

"  the Max10 System Manager contains code for the USB blaster JTAG programmer and that is not free either, that is why it is programmed into the chip but the source code is not available ... "  

        I failed to completely understand the true meaning of your reply in terms of "design limitations".

         Whenever I bought a FPGA development board, whether it be Lattice or Xilinx, I could always download the examples the company supplied to its customers.     Please take notice of this part of the question that I had originally posed:

"  When I looked at the software examples I noticed that they make reference to Quartus Prime Standard, not 'Quartus Prime Lite' ..."

          Can I successfully download the example software using the Quartus Prime Lite and will my programs run as expected?

          Can you also tell me what the "design limitations" will be if I do not have the source code for the MAX 10 System Manager ( a "hands on" example of a design limitation would be helpful for me to understand what the design limitation really is)?

          Thank you for your initial reply.    I gave you a Kudo!    

 

 

 

James_B
New Contributor II
845 Views

Thanks for the Kudo. I do understand the challenges when adjusting between Microblaze and Nios. 

With regards to questions:

1. The Max10 is acting like a USB blaster, and the code for that is proprietary. The Max10 is flash based, and boots from it's own internal flash memory. So when you power up the board, the functionality of the Max10 acting as like a USB blaster that allows you to program the other FPGA on board (in this case Cyclone 10) with just connecting a USB cable to the board and using the Quartus programmer. The Max10 handles the JTAG translations, etc. as it is like an onboard USB blaster. 

2. You are able to download any example code for the board using Quartus Lite for Cyclone 10 LP. You just need to connect a USB cable to the board and have Quartus programmer open. The JTAG signals will go through the on board USB blaster in the Max10 as described in (1) above. I would suggest a basic heartbeat program blinking a LED first before anything to reduce compile time and have a very simple working example, to validate that Quartus is all setup properly. 

Regards, James

TechDeveloper
Novice
836 Views

Dear James;

 

      Thank you for your reply.   You got another KUDO!

       I definitely understood your answer for question 1 and got the "gist" of the answer for question 2.  

      However, the quote below is the context to which question 2 is based:

"...Intel MAX 10 FPGA, pre-programmed System Manager ASSP functions (Not programmable by the user)"

Can anyone tell me what "...(Not programmable by the user)" means in terms of software development limits?

Does this mean that I cannot modify the first stage bootloader or  modify the "control" handoff?    In other words, if there is a problem with the RELEASE version of the download, I can't remedy my problem?

       

James_B
New Contributor II
834 Views

Thanks for the Kudos. I do understand . . . I have had the same issues.

From a high level / top level viewpoint, you will be able to update the RELEASE version of the download if need. 

 

Overall here are the details:  

Basically, there is no First Stage Boot Loader with Nios (compared to something like Zynq 7000 series for example.) The Cyclone 10 LP does not have an ARM A53 or A9 in it . . . so you will have to use Nios and Nios can boot directly from internal memory if the program fits within your internal RAM. For most Nios programs, say 64K to 128Kbytes of memory is sufficient ... and the Cyclone 10 LP should have enough internal RAM (and I believe it also has HyperRam attached to it that you can access) that you should be okay. 

Basically, you can program the flash memory through the USB blaster, and when the FPGA boots the Nios program will be in the flash. You just have to convert the ELF file in Eclipse using mem_init_generate for make targets in Eclipse to convert the ELF to hex, and then attach the hex to your Quartus project and compile ... and the Nios instructions will be in the external flash memory. So in summary: 

1. Develop your C in Eclipse, JTAG downloading your design and testing 

2. When finished, convert ELF to hex with mem_init_generate in Eclipse

3. Attach hex to Quartus project

4. Compile Quartus project

5. Program flash memory with Quartus programmer

When you power cycle, you should see your Nios software executing (such as through Uart, led, etc.)

Regards, James

James_B
New Contributor II
831 Views

I needed to add one more thing: 

1. Develop your C in Eclipse, JTAG downloading your design and testing 

2. When finished, convert ELF to hex with mem_init_generate in Eclipse

3. Attach hex to Quartus project

    3a) Add hex file to on chip memory in Platform designer - memory initialization option

    3b) Add hex file to quartus project 

4. Compile Quartus project

5. Program flash memory with Quartus programmer

When you power cycle, you should see your Nios software executing (such as through Uart, led, etc.)

 

praveenkumar
Beginner
802 Views

hi james , can u help me with the   flashing through genric tri state controller and nios 2 flash programmer  because i got errors with that

like error code 8

and i flashed with the quartus programmer that s working fine by memory initialization.

i have active parallel config nor flash 256mb p3365nm technology

TechDeveloper
Novice
823 Views

James, you are the greatest!!!

You have answered my questions with your fine technical support.  

If you work for Intel Corp, you have definitely been the reason why I am going to purchase the development board.   

Your replies were much appreciated.    You are the greatest!!!

James_B
New Contributor II
821 Views

Thanks for the kind words. 

Overall, I do many projects with development boards as the basis, and design an analog or digital peripheral board to go with the development board in order to prototype a design and deliver a solution to a customer. 

Working with the various development boards and Nios, and figuring out how to program Nios, is not always easy. The Max10 series adds some additional details when programming Nios due to the flash being internal to the part. 

Overall, glad to help. James

Reply