Hello everyone.
I used the tutorial provided on this link
http://www.alterawiki.com/wiki/design_example_-_stratix_iv_qdr_ii_sram_uniphy_400mhz_x18 (
http://www.alterawiki.com/wiki/design_example_-_stratix_iv_qdr_ii_sram_uniphy_400mhz_x18) to get the timing values and I have instantiated this QDR module on QSYS, along with a NIOS II/e processor.
With everything loaded on a on-chip memory, I've attempted to run memory test on the QDR, but it fails at the first bit when checking the data bus.
Another thing that I can't get is: What is the difference between the avl_r and avl_w ports on QSYS? I don't know exactly how to connect them on the NIOS module.
I will attach the qsys screenshot in a few moments.
Any help is appreciated, thank you!
