QSYS Avalon MM Clock Crossing Bridge problems

[Altera_Forum]

I'm using an Avalon MM Clock Crossing Bridge. The problem is that whenever I try to access the remote side of the bridge the NIOS system simply locks up. 

 Did anybody else experience such behavior? Are there any examples available using the clock crossing bridge?   All I want to do is access the native PHY register interface from NIOS.

[Altera_Forum]

Grab SignalTap II and look what is happening on the Avalon bus during your failing operation. My clock crossing bridges are working fine.

[Altera_Forum]

I did already. Both the slave side and the master side of the bridge were dead. It works with a plain bridge, then I observe read getting asserted, etc. But as soon as I replace it with the clock crossing bridge everything will just hang.

[Altera_Forum]

Is there a working mm clock crossing bridge sample anywhere?