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Valued Contributor III
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QSYS changing from Verilog to VHDL

I'm using a modified version of a QSYS processor/peripheral set from an evaluation board as a basis for a new design. I've gotten my design working on the evaluation board using the original Verilog top level design file. Now I want to move the design to my final hardware with a VHDL top level project. 

 

When I look at the generated component instance in the System Inspector tab, it shows the data bus signal type as being a bidirectional "inout". What I really want is a data_in and data_out set so I can route the bus to non-QSYS VHDL modules internally. 

 

When I look at the intermediate files, all the QSYS generated modules and interconnect are in Verilog. Is this just the way it is, or is there a way to generate all these as VHDL with the corresponding VHDL paradigm of unidirectional internal interconnect? 

 

Perhaps there's some setting that I'm missing ....
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Valued Contributor III
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Hi, 

 

Did you get anywhere with this? I am having the same issue. 

The Generation Help text states 

 

 

--- Quote Start ---  

 

You can turn on/off the following synthesis files for generation: 

 

Create HDL design files for synthesis— Creates Verilog or VHDL design files, as specified by the developers of the components and IP cores in the system. The Qsys interconnect fabric uses Verilog HDL code. 

--- Quote End ---  

 

 

Which kind of makes me think it generates Verilog components only. 

 

I would really like a top level SOPC system in VHDL but think I might be stuck 

 

Rgds 

Vern
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Valued Contributor III
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I initially gave up and just wrote the top level in Verilog. Even though the files are allegedly generated in VHDL, they don't have the ports needed to connect them to other internal devices. They can, of course, connect directly to external pins, which is the way they are normally used. 

 

I eventually just rewrote my peripherals as avalon devices and dumped them inside the Qsys system.
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