I'm creating a QSYS component with parameterized address and data bus widths using the 12.0 toolpath.The parameters come up fine, but the signals show -1 as their widths, and the component error/warning window indicates corresponding errors. I can get the design to work fine by eliminating the signal width parameters so this isn't urgent, but I'd like to know how to make this work. Thanks.
So you have something like this correct?
module my_module( address, data, etc... ); // these parameters will get overwritten by the user instantiating core parameter ADDRESS_WIDTH = 32; parameter DATA_WIDTH = 32; input address; input data; etc...If you fed that code directly into component editor you would see -1 settings in the .tcl file for the address and data widths. That tells the tools to run the Quartus II in the background to figure out the widths based on the parameterization. By the sounds of it these values are not getting overwritten and as a result the -1 is getting set in the widths. I would look at the release notes to see if this is a documented bug (it sounds vaguely familiar) but if the fix is to upgrade tools and you don't want to do that I would hand edit the .tcl file and add an elaboration callback that sets the port widths. If you want to see an example take a look at the read master .tcl file and the error signal to see how the callback is adjusting the width of it: http://www.alterawiki.com/wiki/modular_sgdma