Having a problem with the Qsys CFI memory interface: when a CFI interface is added to a Qsys Nios system, there are very important memory control lines that are not "brought out" of the system, specifically the lines shown in the Cyclone III Device Handbook page 9-26 (DCLK, Reset_L, Wait, and ADV_L).How does one get Qsys to present these control lines? To demonstrate the problem create a simple Qsys embedded system with a Nios II CPU, a FLASH and a RAM. Instructions below are for the Quartus II 13.1 Web Edition:
Found the problem:Altera does not support synchronous operations with FLASH memory. Apparently, FLASH memory access is all done asynchronously even during FPGA configuration memory access. So, to make it work, hold the memory's four synchronous control lines (DCLK, RESET_L, WAIT, and ADV_L) in their un-asserted states on the board. A quick review of the Nios Embedded Evaluation Kit (NEEK) will show this being done, with the appropriate pull up resistors. Regarding the errors with the pin assignments, the problem was with the configuration setting for this particular project. To configure an FPGA using a parallel flash with the Cylcone III device, Quartus must be told to use the Active Parallel configuration scheme which is done from the Quartus Assignments menu. So select Assignments - Device, then press the "Device and Pin Options...." button. A new window will appear - choose the "Configuration" category then set the configuration scheme to active parallel. The problem with the project above is that it was set to active serial which made a conflict with the same pins that connect to a parallel flash. We can close the book on this post. Thanks.