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Qsys Custom component Error

Altera_Forum
Honored Contributor I
1,189 Views

Hi  

I'trying to add a custom logic component to my Qsys System using Qsys Pro in Arria 10 environment. 

 

I add the vhdl file (both for synth and simulation) to files panel both it done an error the top_level module does not contains any signals !! (but it is a sinthetizable vhdl....) What is wrong on my procedure ? When I try to analyze the code it gave me an error that Cyclone Gx 10 is missing, but in my Quartus I don' t need Cyclone 10 GX because i'm using Arria 10 ....., there are some parameters to fit on Qsys System to avoid this error? or I should install Cyclone 10 GX libraries?  

 

Regards
0 Kudos
8 Replies
Altera_Forum
Honored Contributor I
239 Views

Is the device in your Qsys system design set correctly, i.e. Arria 10? Maybe the error is because you have your Qsys project set to Cyclone GX 10 and your main Quartus project is set to Arria 10.

Altera_Forum
Honored Contributor I
239 Views

My Quartus project and Qsys project is set to Arria 10, so I couldn;t use a hps in Cyclone 10 because is missing in this FPGA... 

The problem is for every vhdl or Verilog file I tried to insert to Component Editor...
Altera_Forum
Honored Contributor I
239 Views

Any update on this? I see exactly the same problem...

Altera_Forum
Honored Contributor I
239 Views

 

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Any update on this? I see exactly the same problem... 

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I am experiencing this as well. Has anyone received help on this topic?
Altera_Forum
Honored Contributor I
239 Views

I am having the same problem. I tries to a make a new component base don a VHDL design using Qsys. However, the Component Editor displayed an error "top level module does not contain any signals"

TJone2
Beginner
239 Views

The problem persists.

Daixiwen
New Contributor I
239 Views

Did you check the VHDL file for syntax or compile errors first? QSys is less than friendly when it encounters an error while parsing the VHDL file, giving weird error messages. You can try and create an empty project in Quartus, put your VHDL files there and run the synthesizer. Check if any errors are reported, fix them and then try again in QSys.

SSaus
Beginner
239 Views

Hello,

i just stumbled upon the same Problem and found a solution to it. All my ports were discribed in std_ulogic. In this format Platform Manager(qsys) did not recognize the signals.

After chaning them to std_logic they were found. I hope this is helpful even 3 years later. :)

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