Qsys MM modules used a standalone IP cores?

[Altera_Forum]

Hello, 

 Is it possible to use a Qsys module (such as the UART MM component) as a standalone core for a VHDL design? I have a VHDL designa and I"m looking for a basic UART at the moment and in searching for one I keep ending up at the Qsys MM-UART component. I've been trying to get this to work in a VHDL design and it isn't going well. If this is not the way to go could you point me in the right direction to find a simple UART component? I'm using a Cyclone III and there isn't an available one in the Megafunctions wizard either.   Thanks, Rob

[Altera_Forum]

The UART is generated in plain text, so you can take it and modify it however you like. The Avalon-MM Slave is quite contained, and looks easy to remove/bypass should you care to. 

 Alternatively, it is not very difficult to add an Avalon-MM Master port to your standalone VHDL and have it master the UART that way. You might prefer this arrangement in order to avoid having to take ownership of the maintenance of the UART module (but I think that is low risk, since the module is quite simple to start with and hasn't changed recently).

[Altera_Forum]

Ok. So I could write an HDL module to connect to the address, data etc and control the MM UART even though I'm not using nios ii? If I did this, do I just use the API/register information to set bits ect just like I would if I was using C on a nios ii?

[Altera_Forum]

Yes, you can do it that way (I have done the same, with the UART and the SPI, and others). You can build entire systems with Qsys and never use a NIOS or other processor. 

 You will basically end up writing an Avalon-MM Master module, and then have a controlling state machine: initialize the UART control register, wait for IRQ ->read from RX data register; maybe poll the UART status register, etc. Whatever your application needs.  Here is the Altera supplied templates, which are in Verilog not VHDL as you requested: http://www.altera.com/support/examples/nios2/exm-avalon-mm.html