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Honored Contributor I
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Qsys, System Console, running ethernet loopback issue

Hi, 

 

I am using Stratix 5 FPGA development kit. I am trying to check ethernet loopback test mentioned in the 

 

"an647_Single-Port Triple-Speed Ethernet_onboardPHY_RefGuide.pdf".Also we have downloaded the required RTL from the Altera website, compiled the design & downloaded the .sof file. 

We followed the instructions mentioned in the above document. But when i am configuring the PHY 

through config.tcl script, it shows PHY Link down and other messages shown below. 

 

% source config.tcl 

============================================================================== 

Starting TSE MAC Configuration System Console  

============================================================================== 

 

 

 

 

 

 

Info: Opened JTAG Master Service 

 

 

 

 

 

 

Info: Configure TSE MAC 

 

 

 

 

TSE MAC Rev = 0x00000d00 

TSE MAC write Scratch = 0xaaaaaaaa 

TSE MAC read Scratch = 0xaaaaaaaa 

Command Config = 0x0000803b 

MAC Address 0 = 0x22334450 

MAC Address 1 = 0x0000ee11 

Frame Length = 0x000005ee 

Pause Quanta = 0x0000ffff 

RX Section Empty = 0x00001ff0 

RX Section Full = 0x00000010 

TX Section Empty = 0x00001ff0 

TX Section Full = 0x00000010 

RX Almost Empty = 0x00000008 

RX Almost Full = 0x00000008 

TX Almost Empty = 0x00000008 

TX Almost Full = 0x00000003 

MDIO Address 0 = 0x00000000 

MDIO Address 1 = 0x00000000 

Regiter Status = 0x00000000 

TX IPG Length = 0x0000000c 

TX Command Status = 0x00000000 

RX Command Status = 0x00000000 

 

 

Info: Closed JTAG Master Service 

 

 

 

 

============================================================================== 

Starting Marvell PHY Configuration System Console  

============================================================================== 

 

 

Info: Opened JTAG Master Service 

 

 

Info: Configure On Board Ethernet PHY Chip 

 

 

Configure PHY. 

Set PHY SPEED to 1000Mbps 

Enable PHY Auto-Negotiation 

Enable PHY In Full Duplex Mode 

PHY read Control Register = 0x00001140 

PHY read AN Advertisement Register = 0x00000001 

Advertise PHY 1000BASE-T Full Duplex 

PHY read 1000BASE-T Control Register = 0x00000e00 

Set PHY Synchronizing FIFO to maximum 

Set PHY HWCFG_MODE for SGMII to Copper Without Clock 

PHY read Extended PHY Specific Status Register = 0x00008484 

phy link down! 

phy speed and duplex resolve failed! 

PHY operating in Half Duplex mode. 

PHY operating Speed 1000Mbps 

 

 

Info: Closed JTAG Master Service 

 

 

 

 

============================================================================== 

Starting TSE PCS Configuration System Console  

============================================================================== 

 

 

Info: Opened JTAG Master Service 

 

 

Info: Configure TSE PCS 

 

 

TSE PCS rev = 0x00000d00 

TSE PCS write scratch = 0x0000aaaa 

TSE PCS read scratch = 0x0000aaaa 

TSE PCS if_mode = 0x0000000b 

TSE PCS control register = 0x00001140 

Waiting Link Up..... 

Link is established! 

Partner Ability: 

 

 

copper link interface is down. 

Copper operating in Half Duplex mode. 

Copper operating Speed 10Mbps 

 

 

Info: Closed JTAG Master Service 

 

 

 

Please let me know if i am missing anything in proper configuration.Also find attached the design for your reference. 

Please also check from your side and let us know the feedback at the earliest possible time. 

Thanks in advance.
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