Qsys error

[Altera_Forum]

HI , 

 I tried to compile the DE2_115_Media_Computer example that targets DE2-115 board , while compiling Qsys files i am intimated about these errors :  Error: System.External_Clocks.avalon_clocks_slave: Interface must have an associated reset  I am attaching the screen shots of the Qsys file i.e "nios_system.qsys" , i would highly appreciate if any expert on nios ii can help me resolve this error or guide me where to read about this .  Thanks in advance ,  Regards ,  FPGA_guru011

[Altera_Forum]

I think it is fairly explanatory really. 

To elaborate: "There is an 'Error' which is caused because in the system 'System' there is a component 'External_Clocks" which has an interface called 'avalon_clocks_slave' which is required to have an associated reset signal".  So find the component named External_Clocks, which seems to be something you have made (is that correct?). On that component there is the interface mentioned. That is of type Avalon-MM Slave. As per the spec, Avalon-MM interfaces need a reset signal, but you haven't got one. So you need to add a reset signal and associate it with the Avalon-MM slave.

[Altera_Forum]

By the way, which Quartus II version are you using? I remember seeing similar reset related error when upgrade from 13.1 to 14.0 in my other designs. The issue is later fixed in newer Quartus II version. Probably you can try with different Quartus II versions.

[Altera_Forum]

Is this design migrate from another version? or recreate manually in your own quartus 2 version.

[Altera_Forum]

i am using Quartus II ver 13.0 sp1

[Altera_Forum]

Thanks i will follow your instructions and recompile

[Altera_Forum]

--- Quote Start ---  I think it is fairly explanatory really. To elaborate: "There is an 'Error' which is caused because in the system 'System' there is a component 'External_Clocks" which has an interface called 'avalon_clocks_slave' which is required to have an associated reset signal".  So find the component named External_Clocks, which seems to be something you have made (is that correct?). On that component there is the interface mentioned. That is of type Avalon-MM Slave. As per the spec, Avalon-MM interfaces need a reset signal, but you haven't got one. So you need to add a reset signal and associate it with the Avalon-MM slave.  --- Quote End ---    This component was already there , i didnt made it , when open the qsys file it shows me the following signals on External_Clocks : clk_in_primary sys_clk avalon_clocks_slave sdram_clk clk_in_secondary audio_clk vga_clk   There is no reset signal , i can create one as it being pulled from a ready made cores ????

[Altera_Forum]

Just to add  

 clk_in_primary <-- input from clk sys_clk <-- clock output avalon_clocks_slave <-- input from data_master sdram_clk <-- not connected  clk_in_secondary <-- input from clk_27 audio_clk <-- not connected vga_clk <-- output going to VGA controller and VGA_Dual_Clock_Fifo

[Altera_Forum]

https://www.alteraforum.com/forum/attachment.php?attachmentid=11215  

 I am not that familiar with the External_Clocks module that is instantiated in the Qsys system. I don't think they come with Qsys library but rather that comes together with the DE Quartus project. You need to find the hw.tcl file in your local directory. Try to find the avalon_clock_slave and set the proper reset association. Something like:  set_interface_property avalon_clock_slave "associatedReset" "reset"  The "reset" is replaceable by the reset interface being declared in the hw.tcl.