Hello,
I have a Qsys design on ArriaGX which istantiates a couple of DDR2 SDRAM controllers with ALTMEMPHY. This design has been ported from SOPC Builder Version 10.11 Build 197, where it compiled without problems.
Compilation stops with these errors:
Error: Following WYSIWYG I/O primitives are not properly connected to top level pins
Error: padio port of the bidir WYSIWYG I/O primitive "HSFC_NIOS:U9|HSFC_NIOS_ddr1:ddr1|HSFC_NIOS_ddr1_controller_phy:HSFC_NIOS_ddr1_controller_phy_inst|HSFC_NIOS_ddr1_phy:HSFC_NIOS_ddr1_phy_inst|HSFC_NIOS_ddr1_phy_alt_mem_phy:HSFC_NIOS_ddr1_phy_alt_mem_phy_inst|HSFC_NIOS_ddr1_phy_alt_mem_phy_clk_reset:clk|DDR_CLK_OUT[0].ddr_clk_out_p" is not directly connected to a top-level bidir pin
Error: padio port of the bidir WYSIWYG I/O primitive "HSFC_NIOS:U9|HSFC_NIOS_ddr2:ddr2|HSFC_NIOS_ddr2_controller_phy:HSFC_NIOS_ddr2_controller_phy_inst|HSFC_NIOS_ddr2_phy:HSFC_NIOS_ddr2_phy_inst|HSFC_NIOS_ddr2_phy_alt_mem_phy:HSFC_NIOS_ddr2_phy_alt_mem_phy_inst|HSFC_NIOS_ddr2_phy_alt_mem_phy_clk_reset:clk|DDR_CLK_OUT[0].ddr_clk_out_p" is not directly connected to a top-level bidir pin
Where HSFC_NIOS is the Qsys project name, while ddr1 and ddr2 are the controllers.
Has anyone seen this before?
Thanks in advance,
Sergio
