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Qsys to custom HW interface

Altera_Forum
Honored Contributor II
1,011 Views

My FPGA design, including a Nios II, resides mostly inside the Qsys environment. However, I have some custom hardware elements outside of Qsys. I need to pass data and control signals between the two environments, but not having much success.  

 

I tried using an Avalon-MM Pipelined Bridge, exporting the master, but that didn't work. Now I am using a Tristate Conduit Bridge in line with a Tristate Conduit Pin Sharer and Generic Tristate Controller. It seems that the TCB wants to connect to pins rather than internal logic. 

 

Can someone please recommend a good way to connect Qsys with on-chip logic outside of the Qsys environment?
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3 Replies
Altera_Forum
Honored Contributor II
87 Views

What are the requirements of your interface? Timing, throughput, and format all impact the best choice. For simple devices, just use a PIO...

Altera_Forum
Honored Contributor II
87 Views

I am trying to connect Qsys to on-chip logic outside the Qsys environment and would like for the logic to appear to the Nios II SW as a wrtie-able location (such as RAM). In other words, when SW writes to this address it generates an external write signal along with the output data. I also need to read from a separate address. 

 

I use this method to connect to external SRAM with no problem, but it does not seem to work with on-chip logic. 

 

The problem with a PIO is that it does not generate a write signal. I suppose I could create one as on of the PIO bits, but that's a lot of extra SW that I would rather do without.
Altera_Forum
Honored Contributor II
87 Views

If you can do it with SRAM, the same should work with on chip component, too. 

You can expose the master signals or use those of a SRAM interface. 

Is your problem in exporting the interface out of Qsys block or did you implemented and connected everything but it doesn't work? 

The latter is definitely a problem in your component logic or timing related.
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