Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Novice
2,739 Views

Quartus 18.1 + NiosII F on CyclomV : boot fails!

Jump to solution

Hello to everyone !

I have my hardware with Cyclone V 5CSEBA4 , Quartus 18.1 standard licensed. I make a QSYS with an EPCQ64 controller and NiosIIF and I develop my application with Eclipse. It runs well with Jtag ...

 

OK now I want a self boot system!

 

First, I use first NiosII flash programmer utiliy on SBT ECLIPSE, but I received Error Code 8. (this method runs fine with old attempts with some cyclon based development board..)

 

Then, I follow strictly official guide "edh_ed_handbook.pdf" and I attempt to obtain a self-booting hardware from EPCQ64A: "on place" and "boot copier" options. These methods uses Quartus Flash convert utility, that allows to compose a JIC file (Flash Programmer, SOf File, Hex File).

Both files (SOF for FPGA) and ELF for nios runs fine loading then with Jtag. (I use an external SDRAM, tested with Nios QSYS system)

 

Then , I program the chain from QUARTUS FLASH PROGRAMMER on JTAG. It see correctly FPGA+FLASH Chain and program flash correctly.

 

But It's impossible to obtain a bootable system. FPGA starts correctly (Infact If I load the elf from Eclipse, Nios application runs fine).

 

Only difference from manual is on my external SDRAM instead ON CHIP RAM showed in the example, but addressing mode and qsys settings are the same., and My app works fine on external sdram when I test with JTAg and EClipse

 

This is hard problem for our factory! We havent a bootable system today.... :-(

 

Someone can give tips to solve this issue?

 

(ON attach, TEst1 : nios flash programmer->error 8 and TEST2 ->quartus convert test boot copier: it runs but system cannot boot nios)QuartusConvert_BootCopier_Test.jpgAP0001 qsys detal nios-epcq-sdram.jpg

0 Kudos

Accepted Solutions
Highlighted
Employee
82 Views

Hello sir,

Kindly check the following items:

1- Make sure you use a clock source to Serial Flash controller IP (EPCQ) up to 25MHz (MAX).

2- Make sure your Nios II is running at 50MHz.

3- Make sure the MSEL is pointing to the correct flash configuration:

If using QUAD, MSEL should be 10010

If using STANDARD, MSEL should be 10011

 

Please let me know if this could help you.

 

 

Thanks

View solution in original post

11 Replies
Highlighted
82 Views

Hi,

 

Can you try with default settings in convert programming files window.

i.e use hex data -> absolute addressing sof data->auto address. Also comperes sof file.

 

Please attache the .map file for both settings.

 

Regards

Anand

 

 

 

0 Kudos
Highlighted
Employee
82 Views

Please refer to which booting method you using and configure the BSP setting accordingly in here https://www.intel.com/content/www/us/en/programmable/documentation/iga1446487888057.html#fwl14799123..., Nios II Configuration and Booting Solutions, Table26. I would suggest you could start from the flash booting and running code in OCRAM and then move to your booting method, ie flash -> SDRAM. Just use as simple as "Hello world" app code in both tests.

0 Kudos
Highlighted
Novice
82 Views

Nios_settings_for_IN_PLACE_OCRAM.jpgFor Anand:

 

  • If try autoaddress, FPGA dont' boot!.
  • instead, settings SOF with Start/0x00000 FPGA starts correctly.....
  • If loading HEX I select absolute, file converter says me that an overlap occours (obvious, sof starts from 0x000 and I attempt to overwrite it with my hex..)

 

For GNG:

 

I create a simple Nios Application, it handle a flashing led

 

I strictly follow all the guidelines for IN PLACE, ECPQ BOOT

 

On QSYS, I checked connections between NIOS-IIf , ECPQ and OCRAM as per manual illustration Fig. 88

 

I select the offset and vectors as explained on fig. 89, so reset point to ECPQ controller and exception to OCRAM

 

On BSP editor, i follow istructions..

finally, i load the JIC file...

 

FPGA boots, Nios no... :-(

 

Please, there is an idea to solve this terrible issue????

 

 

 

 

0 Kudos
Highlighted
Novice
82 Views

->When I select reset vector to ecpq address, I cannot debug Nios with Jtag, but I think this is normal.. to debug it, I need to restore reset vector to original OCRAM.. so boot is not debuggable anyway...

 

->I checked the epcq_controller2_0.hex, obviously it is very little in size,

about 56k... my onchip ram is 200k so the problem is not here....

0 Kudos
Highlighted
Employee
82 Views

Hello,

If you are looking to boot Nios II from On chip memory (so you can debug in future), you can set the reset and exception vector to onchip memory. then, you can create the hex file from Eclipse. Come back to Qsys, and initialize the Nios II on chip memory with that hex file ( instead of the default initialization).

You need to Enable non-Default initialization file, and select the user created initialization file to the new hex that you have created in EDS.

 

In EDS, if you go to your application folder and create the hex, you will be able to see something like this:

For example, the soc_system_ocram.hex will be used for on chip memory initialization. the trick is you should select the hex file that reflects your on chip memory name in Qsys (please note this is the same memory that you used in reset and exception vectors).

Another file needs to be added to Quartus project is meminit.qip. Once added, you can compile Quartus. The generated sof file should contain the hex within it (no need to add the hex). Now proceed with the JIC creation (add the sof only) and program the FPGA.

 

 

Hope this might help.

 

 

Thanks

 

 

Highlighted
Employee
82 Views

Sorry the attachment didnt appear in my previous note.

Please refer to the attachments below:

 

On chip memory settings:

ocram.JPG

 

 

hex File generation:

 

ccc.JPG

 

Highlighted
Novice
82 Views

Hi! Following "full in place" method proposed by Fjumaah our PCB boots well! I pre-loaded FPGA on chip ram with Hex file generated from Eclipse, then I used Quartus file converter to obtain a JIC file, and after FLASH writing with only SOF file, FPGA and NIOS boots is OK!!!!

 

WELL!!! This confirm that our Hardware runs fine...

 

AND NOW I CLAIM INTEEEEEELLLLLLL ! WE NEEED TO LOAD OUR APPLICATION IN SDRAM , why on-chip is too small for our purposes.

 

If our HW runs fine, and we follow strictly guidelines from edh_ed_handook

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/nios2/edh_ed_handbook.pd...

 

I try boot in place from ECPQ , and boot copier option, but Nios-IIF doesn't boot. Please.... could you give us tips to solve this problem?????

 

I sent a project copy to mr. Anand to examinate this issue.. our hw seems run OK... so Nios should boot from ECPQ...... :-(

0 Kudos
Highlighted
Novice
82 Views

Attempting more options, I found another problem in File Converter/Load HEX file. Error message tell "HEX file overlap memry block 4 to 0) or similar. Reading the forum I found that it is due to Quartus/Assignment/Options/Compiler process settings/More Settings/Read or Write hex files in byte addressable mode.. I had "global" option, I try Byte addressable mode on...

So, BOOT procedure is affected from multiple selection.. Please GIVE US A WELL TESTED PROCEDURE to obtain a BOOT!!!! Final user cannot keep in load own work time to try and solve known bugs.... :-(

0 Kudos
Highlighted
Novice
82 Views

There is anyone about this issue? I cannot believe that there isnt' anyone that have a Cyclone V + niosII processor HW to run! Or this problem afflicts only our system? Passing from Altera to Intel causes many link mismatch and many problems :-(

0 Kudos
Highlighted
Employee
83 Views

Hello sir,

Kindly check the following items:

1- Make sure you use a clock source to Serial Flash controller IP (EPCQ) up to 25MHz (MAX).

2- Make sure your Nios II is running at 50MHz.

3- Make sure the MSEL is pointing to the correct flash configuration:

If using QUAD, MSEL should be 10010

If using STANDARD, MSEL should be 10011

 

Please let me know if this could help you.

 

 

Thanks

View solution in original post

Highlighted
Novice
82 Views

SOLVED! I want say THANKS to MR. Fjumaah. He find quickly some issues on our project with well-maked tests. After these correction (Flash controller clock was too high, set to 25 Mhz, Quad mode was not possible , due to MSEL selection = standard) , ECPQ flash can be seen from Nios SW in Eclipse. After these adjustments, now the system boot correctly with boot copier: it runs fine both to on-chip and to ext sdram.

GREAT

THANKS AGAIN FOR YOUR GREAT SUPPORT

0 Kudos