Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

Question about reset vector!

Altera_Forum
Honored Contributor I
986 Views

I've been simulating a NIOS system in Modelsim, and I've been trying it with the NIOS II e/s/f to compare performance. I noticed that the reset vectors are different depending on which processor I use, and sometimes depending on changes to the software. I'm curious: what instructions are in the reset vector, what is their purpose, and what is different in it due to changing the type of NIOS being used?  

 

Thanks in advance for any assistance!
0 Kudos
1 Reply
Altera_Forum
Honored Contributor I
73 Views

In case anyone is interested about this problem, I received a useful link from Altera that was very helpful... 

 

http://www.altera.com/literature/an/an458.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=an458 

 

All about booting a NIOS II.
Reply